Guest commentary: EDA does support Serdes test

Stephen Sunter, LogicVision -- Test & Measurement World, 1/17/2007 4:50:00 AM

I must disagree with part of T&MW chief editor Rick Nelson’s introductory statement in “ATE adapts to meet SOC test needs” (Test & Measurement World, Dec. 2006/Jan. 2007, p. 19). He writes, “Despite innovative design-for-test (DFT) products from EDA companies, SOC devices will continue to sport high-speed serial, RF, video, and other functions that aren’t readily testable using DFT techniques.”

He is likely aware that LogicVision won the Best Paper award at ITC several months ago for its Serdes test solution, but perhaps he didn’t see the open presentations (available here) that LogicVision gave at its ITC booth showing that the capability described in the paper is commercially available. DFT for high-speed serial I/Os is alive and well.

Serdes IP from at least three different vendors includes DFT that measures the bit-error-rate at almost any position in the received signal eye to deduce the shape of the eye opening. For the last year, LogicVision has demonstrated and successfully sold a purely digital, RTL-synthesized solution that measures everything about any high-speed I/O circuits and signals, from below 1 Gbps to over 10 Gbps. Our ETSerdes can achieve subpicosecond accuracy on any tester because the only connections to the tester are a JTAG port and DC voltages--our 6-Gbps demo uses only an off-the-shelf Altera Serdes FPGA board and a PC.

Stephen Sunter is director of mixed-signal and parametric test at LogicVision.