The analog in software radio: Testing SDRs

SDR modules that mount onto VMEbus single-board computers. The modules contain ADCs, DACs, digital upconverters and downconverters, timing logic, memory, a PCI interface, and an FPGA.

Test the performance of the analog and digital portions of the SDR. Test ADCs and DACs for dynamic range, signal-to-noise ratio, linearity, and intermodulation distortion. Test digital upconverters and downconverters, timing logic, and memory.

• Agilent Technologies: spectrum analyzer, signal generator. www.tm.agilent.com.
• Meterman: handheld DMM. www.metermantesttools.com.
• Pentek: single-board computer. www.pentek.com.
• RLC Electronics: bandpass filter. www.rlcelectronics.com.
• SBS Technologies (now GE Fanuc Embedded): VME-to-PCI bus adapter. www.gefanucembedded.com.
• Tektronix: oscilloscope. www.tektronix.com.
• Wenzel: 100-MHz oscillator. www.wenzel.com.

A software-defined radio (SDR) is a wireless communications system that digitizes modulated signals as close to the antenna as possible. An SDR processes signals using digital algorithms instead of analog circuits. Pentek (Upper Saddle River, NJ; www.pentek.com) produces an SDR dual-channel transceiver.

Each SDR module contains two analog-to-digital converters (ADCs) and two digital-to-analog converters (DACs), one pair for each channel (figure). Because the digital portion of the SDR is in software, the analog portion of the card requires the most testing. Pentek measures many of the characteristics that ADC and DAC manufacturers measure: spurious-free dynamic range (SFDR), signal-to-noise ratio (SNR), linearity, and intermodulation distortion (IMD).

The SDR module attaches to a VMEbus single-board computer (SBC), which attaches to a PC through an adapter. After applying power to the unit under test (UUT), a technician measures voltage with a digital multimeter (DMM). Automated testing begins with a boundary-scan test. Then, the technician moves to analog testing.

The ADC tests include an input-overload-detection test to verify the SDR’s full-scale accuracy and overload signal detection levels. Technicians also perform an ADC channel-synchronization test and a decimation test, which lets them check the programmable decimation stage that follows the ADCs. These tests check both channels using 10-MHz outputs from the signal generator.

SDR modules require rigorous testing of their ADC and DAC analog circuits.

To measure the signal quality of the ADCs, a technician inserts a 70-MHz bandpass filter in series with the signal generator to remove unwanted harmonics and spurious signals from the generator’s 70-MHz output signal. The technician measures the SNR, SFDR, and IMD of the ADCs. The test of the digital downconverter (DDC) uses ADC data to drive the DDC’s input. Output data from the DDC goes to the FPGA, PCI interface, and SBC and then to the PC for analysis.

In a DAC test, the SBC sends a digital baseband signal into the UUT, which sends it through the DAC to both analog outputs. The technicians use an oscilloscope to view the DAC analog outputs in the time domain, and they use a spectrum analyzer to see the outputs in the frequency domain. Technicians also perform digital tests. The external clock test verifies that both external clock inputs are functional and that the operator can switch between internal and external clocks.

“Boundary scan is essential for troubleshooting and testing the many high-density BGA devices on a board,” said Pentek VP Rodger Hosking. “Maintaining adequate analog signal integrity in the midst of digital circuitry is also essential.” Hosking noted that good signal integrity requires clever board layout strategies plus careful assembly, inspection, and testing.