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ICT faces the future as bed-of-nails access erodes

Steve Scheiber, Contributing Technical Editor -- Test & Measurement World, 2/1/2007

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In-circuit test has defied its skeptics since the first analog test systems emerged more than three decades ago. The testers weren’t fast enough. Digital logic would be their downfall. They couldn’t find opens. They couldn’t isolate circuitry sufficiently.

Today, little has changed. Test engineers must deal with denser circuits, eroding bed-of-nails access, higher speeds, and lower voltages, as well as the migration to lead-free solder. Yet, supporters of in-circuit test (ICT) have never wavered. Vendors have conquered each succeeding generation of PCB architecture. Alternatives such as functional test, boundary-scan, and system test have run into their own share of bottlenecks. ICT remains vital to most manufacturers’ strategies for meeting quality targets.

a)  
b)  
a) A bead node can make contact with a flat fixture probe during test. b) No wider than board traces, bead nodes do not compromise circuit density. Courtesy of Agilent Technologies. 
Still, according to Chris Jacobsen, R&D manager for Agilent Technologies, ICT technology is at a crossroads. To survive as a weapon in the board-test arsenal, it will need to make a strategic shift more fundamental than “simple” design-for-testability. The current standard of specifying 35-mil test pads along a 5-mil board trace to accommodate the bed of nails consumes precious real estate and introduces additional fault sites. In addition, the pads are needed only until the board ships. But what choice do you have?

To find a solution, Agilent assembled the In-Circuit Test Measurement Science and New Technology Group, an in-house group consisting of Jacobsen and eight other engineers. Their less-than-obvious suggestion was to reverse the ICT roles of probe and target. Instead of hitting test pads on boards with sharp spring-loaded pins, the group recommended hitting sharp beads on the board surface with flat fixture pins.

Unlike test pads, bead nodes conform to the dimensions of the trace—about 5 mils wide and 15 mils long. The solder-deposition step places an oversized drop of solder on the board trace through an open-mask stencil. During reflow, the wet solder flows along the trace, while its surface tension overcomes gravity, repeatedly creating a sharply pointed feature (Figure 1a).

During testing, a flat 4-oz fixture probe makes contact with the solder bead. The bead’s point begins to flatten into an ellipse until it can support the probe, in the process breaking up any bead contaminants that could interfere with the test. Jacobsen contends that the mechanical effect differs substantially from conventional sharp-pin node penetration. He likens the action to hitting a boiled potato with a frying pan. The potato’s skin breaks up and falls away, exposing the inside.

Figure 1b shows one reason why design engineers will resist including bead nodes far less adamantly than their more traditional counterparts. Bead nodes do not require pushing board traces farther apart, so they don’t compromise circuit density, and they don’t affect the signal integrity of high-speed traces.

It appears that—once again—the report of the death of ICT has been greatly exaggerated.

sscheiber@aol.com

 

PXI module for JTAG test of differential I/O

Goepel electronic’s PXI-5350 3U single-slot module provides 50 bidirectional, differential channels, allowing for the test of differential connectors or backplanes. The test channels are individually programmable as input or output and allow simultaneous driving and measuring. In contrast to conventional boundary-scan I/O modules, the PXI-5350 is not controlled serially through a test access port (TAP) but through a parallel PXI interface to increase test-vector throughput. www.goepel.com

iNEMI to preview roadmap at Apex

The International Electronics Manufacturing Initiative (iNEMI), an industry-led consortium, will preview its 2007 roadmap at this year’s IPC Printed Circuits Expo, APEX, and Designers Summit in Los Angeles. The roadmap will be featured in a keynote session at 8:00 a.m. on Thursday, February 22. The 2007 roadmap will be formally released after March 5, but this keynote session will provide a “sneak peek” at some of the highlights and trends identified by the roadmap. www.inemi.org.

IPC Midwest Conference & Exhibition gains support

In the month following the December 13 announcement of the new IPC Midwest Conference & Exhibition, test-equipment maker SPEA America has joined six other companies in announcing their commitment to exhibit. The event, targeted at the electronics assembly and PCB manufacturing industries, will take place September 23–28, 2007, in Schaumburg, IL. www.ipc.org.

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