Testing strategies for the long haul: Verigy’s Barnes on semiconductor test (continued)

A continuation of our interview with Keith Barnes, CEO and President, Verigy, which appeared in the April 2007 Viewpoint column.

Larry Maloney, Contributing Technical Editor -- Test & Measurement World, 4/1/2007 12:01:00 AM

Click here to read the first part of the interview.

Keith Barnes CEO and President Verigy Cupertino, CA Keith Barnes assumed responsibilities as president and CEO of Verigy in May 2006. Prior to taking this position, Barnes was chairman and CEO of Electroglas, a leading company in IC probe manufacturing, and before that, he was chairman and CEO of Integrated Measurement Systems (IMS), an Oregon-based company specializing in mixed-signal and memory-IC verification that was acquired by Credence Systems in 2001. Barnes is active in numerous industry associations, serves on the boards of Cascade Microtech and Clarity Visual Systems, and is a regent at the University of Portland. Contributing editor Larry Maloney spoke with Keith Barnes about automated testing trends in a recent telephone interview.

A: We have a very rich history of driving costs down through integration. As customers increase the size of their gate counts and pin counts and make their devices more complex, we continue to integrate our test products to offer more pin counts and higher speed at a lower price. As they pack more power into their chips, we use the same methodology to pack more capability into our test equipment to keep costs down.

As already noted, our single scalable platform strategy also is very important in this effort to curb test costs. The V93000 platform for SOC was first introduced in 1999. We’ve added new data cards and other enhancements since then, but those first systems are still meeting customer needs. In contrast, some of our competitors change platforms every 18 months to 3 years. We’ve been able to “break the code” and just switch out data cards in the mainframe. After the mainframe has been depreciated, all our customers have to do is put in new cards to upgrade.

The software also stays intact, which means that you don’t have to retrain engineers. Finally, there is more savings in loading. Outsourced assembly and test companies, for example, can put in the old or new data cards and keep the systems well loaded. With Verigy equipment, customers can test both older and new parts on one system.

Q: What are the benefits of using Verigy’s Pin Scale HX high-speed extension card for testing SerDes (serializer/deserializer) circuits?

A: There are a number of built-in-self-test tools for SerDes. They do a good job of verifying the functional operations, but they lack the capability for doing timing accuracy, or the type of timing accuracy required to verify the parametric operation. Today, serial interfaces have speeds of around 5 Gbps, and are moving to 8 to 10 Gbps in the near future. Coupled with migration to smaller geometries, that trend has resulted in less margin between device specifications and the actual silicon, mostly in jitter measurement. So, very precise timing measurements are required at speed to verify that the device meets specs. The value of the Pin Scale HX option used with our V93000 SOC tester is that it enables those measurements.

Q: In general, what factors will continue to fuel demand for full-featured automated test equipment (ATE), versus built-in self test or design-for-test techniques?

A: Although there are a number of good DFT and BIST products available from EDA vendors, there will still be the need for functional test. Even though customers have been able to use these tools to check out certain elements of the IC that they’re building, they can’t check out the entire device. There are overall timing issues in these complex parts that only functional test can really get at. What we see is a combination of BIST and functional test as the methodology that manufacturers are using now and will continue to use for some time to come.

Another area, which is particularly not well supported by BIST tools, is analog or mixed signal. I’ve had discussions with EDA vendors and with other people in the industry, and there is very limited activity on mixed signal and analog. So, we continue to need a full-featured set of ATE for testing analog or mixed-signal devices. We’re happy to work with customers on this issue. It’s an interesting and difficult challenge.

Q: Speaking of EDA firms, can you give some examples of how Verigy is partnering with other vendors to develop cost-effective test solutions?

A: For one thing, we’re driving a joint effort for standardization of volume diagnostic datalogging. We have a close working relationship with Cadence, Mentor Graphics, and Synopsys* to enable efficient volume diagnostics flows. There are many faults that occur in manufacturing in smaller geometry devices, and the data that’s transferred back from the testers for analysis to the EDA tools must be the most important and smallest subset of data. To make sure that this process works most efficiently, we work with EDA companies to make certain that the necessary data gets reduced and formatted the way it needs to be.

As another recent example of collaboration, we have teamed up with Test Insight, which has extensive experience in developing DFT solutions, to develop a fully STIL-compliant reader/writer for creating debugging test programs used with the V93000.

Q: How is the decision-making process changing for ATE purchases?

A: There are a lot of different models out there. Our IDM and fabless customers do most of the design verification, and typically these customers buy their own equipment. In cases that involve outsourced assembly and test (OSAT) companies, the semiconductor companies will often buy the equipment and consign it to the OSATs, or contracts will specify that the OSATs will place their orders with specific ATE vendors. So, IDMs and fabless companies continue to play a strong role in recommending ATE equipment. That’s one of the reasons why we’ve focused our efforts on capturing the top IDMs as our customers. If a really difficult device is being produced for the first time, which ATE system is a developer going to feel the most comfortable recommending to downstream test partners? It is typically the one that they have most confidence in, and that is typically the one they used in the design-verification process.

Q: How is the rising influence of Asia in the semiconductor industry influencing Verigy’s strategies?

A: Certainly, Asia continues to grow in importance for the industry and for our company as a center of gravity for testing. Our business in Asia is increasing, both for testing new designs as well as for high-volume manufacturing. We have major operations in China, Japan, Taiwan, Korea, and Singapore, and in each instance we have managers in place who are from those countries. We clearly have a very Asia-centric view of the world for HVM. Verigy is currently manufacturing our memory test systems outside of Shanghai with Flextronics, and we have announced that we’ll be manufacturing our SOC products in China as well.

Click here to read the first part of the interview.