Time-to-market pressure drives parallel parametric test
Parallel Test Technology: The New Paradigm for Parametric Testing, 1st ed., Keithley Instruments (ggcomm.com/Keithley/PPTHandbook.html), 2006. 60 pages. Free.
Rick Nelson, Chief Editor -- Test & Measurement World, 5/1/2007
No part of a product life cycle is immune to time-to-market pressures, and that includes wafer-level parametric tests on scribe-line test structures. Parallel parametric test is emerging as a technique that can not only cut test times but also optimize the use of instruments within a parametric test system.
As the handbook Parallel Test Technology points out, parametric test systems are typically equipped with multiple source-measure units. Assuming a full complement of eight such units, seven will sit idle during sequential test of a simple resistor. With parallel parametric test, the remaining seven can be deployed to simultaneously test a couple of transistors and a diode, for example.
The handbook provides clear guidelines on implementing parallel test. For example, it advises that, at least initially, parallel parametric test should be applied to structures located within a single test element group (a group of capacitors, inductors, transistors, and vias, for example, that together help evaluate specific failure modes).
The book also recommends that you establish a measurement baseline using sequential test before performing parallel test, that you use caution when introducing parallel test on legacy test structures that have shared terminals, and that you take note that prober overhead can adversely affect parallel-test time savings.
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The shared-gate configuration in this legacy test structure prevents source-measurement units SMU1 and SMU2 from independently driving the two transistors’ gates. |
A subsequent chapter discusses ways to optimize the design of test structures to facilitate parallel test (for instance, employ layouts that minimize parasitic resistance) and estimates the time savings that can result.
The book helps relate parallel test to other test considerations. For example, a sidebar in chapter 1 contrasts parallel test with adaptive test (a results-based approach that determines the number of sites to be tested and the number of tests to be performed based on previous measurements) and advises against ramping up parallel and adaptive test at the same time.
The book cites Keithley’s S680 DC/RF parametric test system from time to time, and an appendix focuses on parallel test implementations using the company’s pt_execute program, but the bulk of the information presented is generic.
