Probe-mark inspection

Probe marks result from the physical contact between the probe tip and the bond pad during electrical testing, usually after the wafer-fabrication process is complete. Although some marking is unavoidable, manufacturers have discovered that excessive marking can have an impact on yield and device reliability and, therefore, must be closely controlled. In fact, large, deep, or misplaced probe marks can result in poor adhesion with the wire bonds used for connections between die in multichip packages, and this poor adhesion is one of the primary causes of yield loss in multichip devices.

Multichip packages have become popular because of the need to increase memory density in a range of applications and because manufacturers of handheld devices (such as cell phones) often want to combine logic and several kinds of memory in the smallest possible physical package.

The automotive industry is also finding that probe marks can have an impact on reliability, and with the industry’s emphasis on “zero-defect programs,” many auto manufacturers now require 100% probe-mark inspection.

Other trends also contribute to the growing demand for probe-mark inspection. Advanced fabrication processes use low-k dielectrics that, depending on the particular material used, are either softer or more brittle than conventional dielectrics and are, therefore, more easily damaged or deformed by the probe. In the continuing drive to put more circuitry in a smaller area, designers have opted to position bond pads over active circuitry, so excessive marking or punch-through can damage the circuit directly. Advanced bond-pad designs often incorporate a copper layer or post, which can shed material during the probing process, resulting in copper particulate contamination elsewhere.

The cost of probe cards has escalated tremendously—in some cases to more than $200,000. Correlating probe marks with probes allows engineers to monitor the condition of individual probes and repair or rework them before damage is irreversible. Some manufacturers are implementing pre-probing bond-pad inspection in order to protect expensive probes from the damage that contaminated or improperly formed pads might cause.

The increase in demand for multichip packages is driven by increased consumer demand in several different sectors. Some things you can never get enough of—for computers and electronics, one of those things is memory. A number of new product introductions illustrate the surge in demand for memory, among them the powerful Xbox 360 and PlayStation3 gaming systems, and Windows Vista, with its requirement for gigabytes of DRAM and sizeable flash memory to support the quick boot capability.

A second trend driving demand for multichip packaging is the evolution of the cell phone from a simple communication device to a multifunctional handheld personal entertainment system incorporating such disparate capabilities as still photography, video and audio recording and playback, gaming, text messaging, e-mail, Web browsing, and personal digital assistance. These features require system-in-package (SiP) devices that combine multiple chips of different types—SRAM, DRAM, flash, logic, analog, and radio frequency—in a single package of minimal size. For example, the FreeScale PCM29415 SiP includes a FreeScale baseband processor, two Intel NOR flash chips, and a Samsung DRAM chip.

A third contributor to increasing demand for electronic devices, some of which are in multichip packaging, is the automotive industry. Latest generation vehicles contain tens and sometimes hundreds of integrated circuits. The growth trend is expected to continue, with the demand for additional safety and performance enhancements such as side-impact airbags, antilock braking systems, and traction control; increases in cabin and cockpit electronics for entertainment and navigation; and additional communication capabilities including satellite and wireless.

Figure 1. Probe-pad problems, and in particular damage caused by contact between the pad and the electrical test probe, are a primary cause of failure in wire-bond interconnects. In this example, the probe marks cover more than 25% of bond pad area and have exposed under-lying passivation. Courtesy of Rudolph Technologies.

In particular, damage caused by contact between the pad and the electrical test probe (Figure 1) is a primary cause of failure in wire-bond interconnects. Failure modes include excessive marking, which interferes with the bond reliability; punch-through, which reduces bond reliability and exposes underlying circuitry to the bonding process; and etch defects, in which overlying passivation is not completely cleared from the bond pad.

Another issue of growing importance is vendor accountability. Many SiP devices incorporate chips from different vendors. SiP integrators do not want to be held responsible for defects that occurred upstream in the supply chain, and many are implementing incoming probe-mark inspection or imposing requirements for outgoing inspection on their suppliers, or both.

New processes and materials—such as low-k dielectrics—being implemented at advanced technology nodes (65 nm and below) are also increasing the need for probe-mark inspection. This vulnerability is exacerbated by the relentless drive to put more circuitry on smaller die and the resulting trend to locate active circuitry beneath bond pads.

Figure 2. Probe marks are only one of several mechanisms that can cause wire-bond failures, and an inspection system must be sensitive to the broadest possible range of defects. In this case, the pad shows evidence of corrosion. Courtesy of Rudolph Technologies.

Recent developments in testing technology are also contributing to the demand for probe-mark inspection. There is significant incentive to reduce any risk of damage to probe cards, such as might be caused by particulate contaminants on the probe pad. A number of manufacturers have implemented pre-probe inspections to minimize this risk. Probes wear during normal use but may be reconditioned or repaired up to a certain point. Careful analysis of probe marks can provide information that signals the need for reconditioning of a probe.

Another trend in test technology is the movement of electrical testing upstream, into the fabrication process, to allow faster detection, diagnosis, and correction of defective processes. Though faster feedback is always desirable for process control, the need has become more urgent as the fraction of defects that cannot be detected with conventional in-line inspection techniques has grown at each successive technology node. Limiting, or at least detecting, probe-induced damage in the earlier stages of wafer processing will play an important role in the successful integration of electrical test into the fabrication process.

Figure 3. Confocal microscopy can provide for the detailed review and characterization of probe marks. In this example, the mark is well resolved in three dimensions, and a breakthrough to underlying layers is clearly shown. Courtesy of Hyphenated Systems.

The probe-mark inspection process must be capable of evaluating a number of quantitative and qualitative characteristics. Quantitative measures include size, location within the pad, proximity to the edge of the pad, orientation relative to the center of the pad, and orientation trends across the wafer. Qualitative indicators include over-etch and under-etch, pitting, corrosion, abrasion, roughness, and punch-through. Advanced automatic defect classification (ADC) that makes efficient use of all available input to provide fast accurate classification is a practical requirement for probe-mark inspection in a production environment.

The use of multichip packages is increasing, driven primarily by consumer demand for larger memory, multifunction handheld devices, and increased electronic capabilities in automobiles. The primary first level interconnect technology in multichip packages is wire bonding. Probe marks created by electrical testing are a primary cause of failure in wire bonds. Probe-mark inspection is playing an increasingly important role in maintaining the yield and reliability of wire-bonding processes.