Scalable pattern-conversion software
Staff -- Test & Measurement World, 6/1/2007
Test Systems Strategies Inc. (TSSI) has announced two pattern-conversion software products, TD-Scan and TD-Sim. Both products can be configured to support all popular ATE platforms, performing tester rule checking for each ATE model before generating ready-to-load ATE files.
TD-Scan supports ATPG outputs with compression technologies from Cadence, Mentor Graphics, and Synopsys; it is designed to translate ATPG scan patterns in WGL or STIL format to a target ATE program format. Since scan patterns come with timing, the translation is made by a quick syntax-conversion process. For functional patterns in Verilog Change Dump (VCD) or Extended Verilog Change Dump (EVCD) format, TD-Scan can be upgraded to TD-Sim.
TD-Sim supports Verilog simulation outputs from several EDA vendors. The software is designed to translate both scan patterns and functional patterns from logic simulators in the format of VCD or EVCD event files. A waveform-based cyclization engine can automatically detect clocks and cyclize E/VCD files with a push of a button. Various filters are also available for those event files requiring conditioning before cyclization.
Base prices: TD-Scan—$5000 per year on a subscription basis; TD-Sim—$15,000 per year on a subscription basis. Test Systems Strategies Inc., www.tessi.com.
