Vendors pursue new DFT strategies
Report from the 2007 Design Automation Conference, June 4-8, San Diego, CA.
Richard Quinnell, Contributing Technical Editor -- Test & Measurement World, 6/6/2007 9:11:00 AM
The major design and test system vendors, including Cadence, Mentor Graphics, and Synopsys, are pursuing design for test (DFT) along several fronts to accommodate the changing role of test in semiconductor manufacturing. Originally, semiconductor test focused on finding random fabrication defects due to dust, but with today’s designs, vendors agree, feature-dependent defects are beginning to dominate. These defects result from complex optical interactions that occur while transferring the mask pattern to the semiconductor. They have become increasingly more common as process geometries shrink below the wavelength of light used in the photo-lithography.
The major vendors all have tools that allow test engineers to perform what some call "volume diagnostics" and others refer to as "defect diagnostics." Whatever it is called, the tools gather data on errors found during the test of many devices, then make that data available for engineers to analyze and determine the types of nets, cells, and other on-chip structures that are involved. This knowledge can then be used to increase production yields by revising error-prone sections of the layout.
Three other test areas have drawn considerable attention from vendors. One is testing for small delay defects. These are marginal rise-times and other timing variations that are not large enough to be detected using conventional techniques but may surface as errors during field deployment. Timing-aware automatic test pattern generation (ATPG) software from the major vendors adds vectors and on-chip clocking cores to explore timing in fine detail on select nets.
A second test area drawing attention is the control of test for low power designs. Simply shifting test vectors into a scan chain can exercise the gates of a low-power design much faster and more often than its expected field operation. Exercising the device while maintaining it's low power operation requires the appropriate use of on-chip clocking gates and independent testing of different power zones. The major vendors all have tools that provide the extra care that low power designs require.
Third, vendors are providing tools to implement the compression of test vectors in an effort to shrink vector size and reduce test time. The increasing complexity of designs along with new test needs has caused test vector sets to balloon, increasing test costs. Compression utilizes blocks embedded in a device's scan test chain that can generate large sections of a test vector from a relatively small number of bits. The blocks may also reverse the process for the test result output. The result of compression is faster testing and lower tester memory requirements. Compression rates of 100X or more are routinely being achieved and further improvements are in the works.
