Summit to cover gamut from cost control to RF test
-- Test & Measurement World, 6/27/2007 7:32:00 AM
At the SEMI Test Summit and Reception at Semicon West, executives from five semiconductor ATE companies will join moderator Rick Nelson, chief editor of Test & Measurement World, and host Ashoke Seth, test operations director at Intel, in a discussion focused on meeting the design, test, and yield requirements for advanced semiconductor manufacturing.
Panelists will include R. Keith Lee, president and CEO, Advantest America; Lavi Lev, CEO and president, Credence Systems; Tim Moriarty, president, Nextest Systems; Mark Jagiela, president, Teradyne Semiconductor Test Division; and Keith L. Barnes, president and CEO, Verigy.
Topics discussed will run the gamut from business conditions to technical challenges, based on pre-event interviews with the participating executives. On the business side, Moriarty cited the adoption of the “fab lite” model and the rising manufacturing prowess of China as topics worthy of discussion. Jagiela commented on overall cost of test, noting that test-equipment capital expenditures for non-memory device test have fallen from 4% of semiconductor revenue 20 years ago to 2% today. He added though, that the customer base doesn’t perceive that to be the case—for reasons he’s prepared to elaborate on during the summit.
On the technical side, several participants cited the test challenges that RF circuitry poses when integrated into SOCs. Advantest’s Lee said it’s getting easy to drop RF circuitry onto a substrate but that testing that circuitry is a complex task. Lev of Credence said that increasing RF integration will require test systems that are flexible and that can be easily adapted to specific customer requirements. And Jagiela said mixed digital and RF devices pose challenges in deciding whether to use an “uber tester” for single-insertion test or to distribute test among multiple test systems. Verigy’s Barnes didn’t want to speak on the record on the topic in advance of the event, but Verigy’s RF direction is suggested in its June 26 introduction of the Port Scale RF card for the V93000 SOC test platform.
Also up for discussion will be the role that test can play in fine-tuning semiconductor processes for yield enhancement. Lev predicted a significant role, saying that test will be essential not only for monitoring yield but also for determining yield. Jagiela predicts a more incremental role for test in this area, commenting that most problems will need to be fixed in device models and layout tools before they can slip through to test.
The summit will take place Wednesday, July 18, 5:30 p.m. to 7:00 p.m. at the Moscone Center, West Hall, Level 2. A reception will follow the panel discussion.
The event is free for all registered Semicon West visitors. Advanced registration is required. Click here to register.
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