Guest commentary: The technology driving Instrumentation 2.0—PCI Express
Murali Ravindran, National Instruments -- Test & Measurement World, 6/27/2007 8:48:00 AM
Editor’s note: This article is part 2 in a series on Instrumentation 2.0. Read part 1 (the introduction) and part 3 (on FPGAs).
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Murali Ravindran |
As devices evolved, higher performance bandwidth-intensive devices began starving other devices on the same shared bus. Gigabit LAN cards, for example, can monopolize up to 95% of available PCI bus bandwidth. Figure 1 illustrates the bandwidths and latencies of various buses, including PCI Express. (Go to Figure 1.)
To provide the bandwidth required by these modern devices, PCI Express was developed by an industry consortium of PC and peripheral vendors and began shipping in standard desktop PCs in 2004. Today, most PCs from leading suppliers have multiple PCI Express slots with varying lane widths.
The most notable PCI Express advancement over PCI is its point-to-point bus topology. The shared bus used for PCI is replaced with a shared switch, which provides each device its own direct access to the bus. And unlike PCI, which divides bandwidth between all devices on the bus, PCI Express provides each device with its own dedicated data pipeline.
Data is sent serially in packets through pairs of transmit and receive signals called lanes, which enable 250 Mbytes/s bandwidth per direction, per lane. Multiple lanes can be grouped together into x1 (“by-one”), x2, x4, x8, x12, x16, and x32 lane widths to increase bandwidth to the slot.
PCI Express dramatically improves data bandwidth compared to PCI buses, minimizing the need for onboard memory and enabling faster data streaming. For instance, with a x16 slot, users can achieve up to 4 Gbytes/s of dedicated bandwidth, as opposed to the 132-Mbytes/s shared across all devices of the 32-bit, 33-MHz PCI bus.
One of the key elements driving the rapid adoption of PXI is its use of PCI in the communication backplane. Now, as the commercial PC technology is evolving from PCI to PCI Express, PXI has the ability to meet even more application needs by integrating PCI Express into the PXI standard. By taking advantage of PCI Express technology in the backplane, PXI Express increases the available PXI bandwidth from 132 Mbytes/s to 6 Gbytes/s for a more than 45X improvement in bandwidth while still maintaining software and hardware compatibility with PXI modules.
With this enhanced performance, PXI can reach into many new application areas, many of which were previously only served by expensive and proprietary hardware. For example, with PCI Express, a digitizer achieves a direct path to the CPU module, through either an embedded controller or an MXI controller to a PC, with a bandwidth of 1 Gbyte/s. This is approximately an 8X improvement over the throughput offered by the 32-bit, 33-MHz PCI bus. Thus, with PCI Express technology, a high-resolution 16-bit IF digitizer or generator can potentially stream continuously to the CPU at bandwidths up to 500 MHz without bus limits or sharing bandwidth with adjacent modules.
Backplanes offering hybrid PXI and PXI Express slots (such as the eight-slot backplane shown in Figure 2) preserve compatibility with existing PXI modules. In addition to providing hardware compatibility through hybrid slots, PXI Express systems also provide software compatibility so engineers can preserve their investment in existing software. (Go to Figure 2.)
PCI Express software compatibility is guaranteed through the PCI Special Interest Group (PCI-SIG), which includes companies like Intel and Dell. Because PCI Express uses the same driver and OS model as PCI, the specification guarantees that engineers have complete software compatibility among PCI-based systems (for example, PXI) and PCI Express-based systems (for example, PXI Express). As a result, both vendors and customers do not need to change driver or application software for PCI Express-based systems.
By maintaining software compatibility between PCI and PCI Express technology, the specification drastically reduces cost for vendors and integrators to insert new PCI Express technology into existing test systems. With hardware compatibility provided by the hybrid slot and software compatibility, the cost of adding PXI Express technology is minimal.
PXI Express not only retains the timing and synchronization features of PXI, it also adds several new synchronization features by taking advantage of the existing differential connectors required in PXI and by taking advantage of technological advances that provide higher performance, low-cost differential signaling. Building on these existing capabilities in PXI, PXI Express provides the additional timing and synchronization features of a differential system clock, differential signaling, and differential star triggers.
High-performance capabilities of the PCI Express technology extend to solve a variety of new applications. Specifically, in automated tests for the military and aerospace industry, the high-bandwidth, lower latency PCI Express bus available in PXI Express opens doors to many new applications which were previously served by expensive and proprietary instruments:
• high-bandwidth IF instruments for communications systems test;
• interface to high-speed digital protocols including LVDS-based proprietary protocols, FireWire, and Fibre Channel;
• large-channel-count data-acquisition systems for structural and acoustic test;
• high-speed image acquisition; and
• high-speed data streaming.
PCI Express is a key technology enabling the fundamental change to Instrumentation 2.0. Engineers and scientists now have the option of transitioning from fixed-functionality stand-alone systems to flexible software-based systems that can be redefined by the user. PCI Express makes this possible by providing a higher bandwidth, lower latency, lower cost, and backward-compatible bus for instrumentation systems.
Murali Ravindran is a product manager for PXI remote controllers at National Instruments. Ravindran holds a master’s degree in electrical engineering and an MBA in entrepreneurship from the University of Oklahoma.
More on Instrumentation 2.0:
• Read part 1 of this multipart series, "PCI Express, multicore processors, and FPGAs drive Instrumentation 2.0."
• Read Chief Editor Rick Nelson's April Editor's Note on Instrumentation 2.0.
• Read related blog commentary.
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