Semicon West speaker highlights critical test challenges
Rick Nelson, Chief Editor -- Test & Measurement World, 7/17/2007 4:27:00 PM
San Francisco, CA. “Critical Issues in Test” was the title of a special TechXPOT presentation 3 p.m. Tuesday July 17 at Semicon West. Octavio Martinez, director of test engineering at Qualcomm, kicked off the session by describing the technology his firm, founded in 1985, has employed in growing to be the largest fabless semiconductor company in the world. "We generate ideas, and those ideas eventually get made into silicon," he said, going on to describe a "virtuous cycle" in which revenues get fed back into R&D.
Qualcomm chips have everything, he said—DSPs, RF circuits, microprocessors (such as the 1-GHz, 250-mW Snapdragon), graphics processors, and memory. He said that Qualcomm began with 130-nm processes and has now taped out designs at 45 nm, resulting in lower power, lower cost chips that bring laptop functionality to a handset.
To test future chips, he said that Qualcomm is looking to improved DFT solutions, thorough silicon validation, and extended presilicon validation with a manufacturing focus. He called on test vendors to offer scalable test platforms that would support characterization as well as production test. In addition, he expects to use more signature-based testing, which he described as a “smart matched loop on steroids.” He is looking to extend multisite testing, which will pose a challenge to test vendors because a single SIP may integrate as many as 12 radios. Also on his tester wish list is a universal pin that would handle signals from DC to RF.
He emphasized system-level regression testing of Qualcomm chipsets, which may have in excess of 100 clock domains. ATE, he said, is very synchronous, and regression testing provides a way of coping with Qualcomm chipsets' asynchronous nature.
He focused throughout his presentation on yield, and called for real-time yield learning with zero overhead. Qualcomm has made progress in yield, he said, noting that it took the company 1 million wafers to get target yields at 130 nm but only 2000 wafers at 65 nm.
But the bottom line, he said, is cost. First, he said, vendors must maintain backwards compatibility to protect the investment in the installed base. Further, he said that ATE capital expenditures have not been falling in concert with chipset average selling prices. Cost of test, he said, must be no more than 6% of raw silicon acquisition cost. He concluded that, "ATE makers must keep up with relentless pressure to reduce cost of test."
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