ITC tackles nanometer test challenges
Rick Nelson, Chief Editor -- Test & Measurement World, 9/12/2007 4:27:00 AM
Adaptive test, power-aware test, and advanced diagnostics will be among the topics covered in International Test Conference events to help attendees meet nanometer test challenges. The conference and associated Test Week presentations, to be held October 21-26 in Santa Clara, CA, will also address the latest innovations in traditional ITC subject areas ranging from microprocessor test to board and system test.
In a recent telephone interview, Janusz Rajski, ITC program chair and Mentor Graphics chief scientist and director of DFT engineering, provided more details on what attendees can expect.
Q. This year’s theme is “facing nanometer test challenges.” Could you elaborate on that?
A. We have noticed that lot of the challenges we saw in the past are compounding when we go to 65 nm and below. Issues related to power and to the staggering complexity and small feature sizes of 65-nm devices add new types of defects—including systematic defects—that can impact yield.
Q. How, specifically, is the conference addressing this theme?
A. You’ll see, for example, that on Tuesday Gadi Singer of Intel will deliver the keynote address, “Meeting the Challenges at the Extreme Ends of the Spectrum—Nanotechnology and Giga Complexity.” He will emphasize the test challenges posed by small feature sizes and by issues related to tremendous complexity that is now integrated into a single device.
Also on Tuesday Ken Butler of Texas Instruments will deliver an invited address titled “Pinning Down This Elusive Thing Called Adaptive Test.”
Q. Could you provide a brief definition of adaptive test?
A. Adaptive test is an approach where you want to figure out the most frequent and prevailing ways in which devices fail. It is a type of profiling that helps you develop your tests to maximize the coverage of those most likely defects. With adaptive testing, you are usually doing some testing as well as some analysis. As you learn from this analysis, you try to develop subsequent tests that are even more effective.
Q. By the way, what is the difference between a keynote address and invited address?
A. The keynote address will be presented during the Tuesday morning plenary session. But each afternoon—Tuesday, Wednesday, and Thursday right after lunch—will feature an invited address. We adopted that format last year, and attendees liked it. It gives everyone a chance to convene in one location and exchange observations from other sessions. Also, we want to provide an irresistible program that gives our Silicon Valley attendees an additional incentive to attend each day.
Q. What are the other two invited addresses?
A. On Wednesday, Al Crouch of Inovys will speak on “The Need for Standard and Efficient Interconnection and Access of Embedded-Everything.” He will discuss not only DFT but also, for example, the access required for silicon debug. And on Thursday, Gordon Roberts of McGill University will present a talk called, “What’s The Trouble with Analog/Mixed-Signal Test—Not Enough Feedback.”
Q. What’s different about the technical sessions this year?
A. The focus of the sessions is shifting to issues that we wanted to highlight in the theme. One of those is power-aware test. Power is not a new issue, but it is becoming a more and more important issue. There are a lot of power-related structures being introduced, like clock-gating, and there are also issues related to power standards introduced by the EDA industry.
A second area is quality of test and how to combine multiple techniques to reduce test escapes. Quality of test has become once again a very hot topic, in part driven by the automotive industry and its requirements for 0 DPM and very low cost of test—two extreme and contradictory conditions. A number of related sessions will focus on small delay defects caused by power and voltage droop.
Another area we are emphasizing with the technical program this year is advanced diagnosis, especially with links to the physical domain, to be able to perform volume diagnosis from manufacturing test data. The goal is not only to diagnose to the gate level but down to the level of specific features on the layout. Done in high volume, advanced diagnosis can help in the calibration of DFM rules and in the development of recommendations and guidelines.
Of course, we also have strong sessions in the areas we have traditionally covered. Attendees at these sessions will learn about the latest test techniques related to microprocessors, SOCs, delay test, test compression, analog and mixed-signal devices, RF devices, SERDES, PLLs, and memories. We also have sessions on ATE and board and system test. These topics are well established within the ITC and remain popular as presenters push the state of the art each year.
Q. Could you comment on this year’s workshops?
A. We have three this year, scheduled for Thursday and Friday. One is on design-for-manufacturability and yield. It is a continuation of successful event last year, which focused on SOC manufacturability and design-specific optimization. This is a very important area in which test has a role to play. It provides an opportunity for test to offer additional value as companies move toward volume diagnosis, where they test thousands of parts per day and derive from the collected test data statistics that are useful for adaptive testing.
A second workshop, on current and defect-based testing, continues a successful event from last year. It focuses on understanding how devices fail so that test can be optimized to improve quality of test and minimize cost.
Finally, we have a one new workshop: “ATE Vision 2020.” This workshop promises to be a very interesting one because it is going to examine the long-term trends in ATE architecture.
Q. What other programs are offered in this year’s Test Week?
A. We will continue to have two days of tutorials, on Sunday and Monday, covering such diverse topics as design-for-manufacturability, failure analysis, quality-of-test for nanometer devices, analog mixed-signal test, RF test, memory test, SIP test, wafer probing, and IEEE 1500.
We will also continue supplementing our program with a series of lectures, which cover fundamental as well as leading-edge topics. We have four lecture sessions. One is on boundary-scan based system test. Another covers power issues in test and case studies. We have found that people love case studies because of the wisdom they can derive from them. Another lecture will cover system test strategies, and a final one will cover reliability and test.
Related to lecture series, this year we are introducing a new forum, which we call “advanced industrial practices” sessions, which will focus on the latest techniques used by industry leaders. We will have four of these sessions, including one on the latest in wafer probe technology—where it is, where it is heading, and how people use it in conjunction with compression to do multisite testing. Another will cover statistical methods to improve test-floor operations and provide practical advice in cost reduction, chip bring-up, and yield enhancement.
Q. ITC is returning to Santa Clara this year. What is the geographical distribution of submissions?
A. We are noticing some interesting changes. Not surprisingly, most submissions came from the US, but we are seeing many more submissions from Asia. Japan was number 2, followed by China, Taiwan, and India. Obviously, that is a different very picture than we have had in the past, and much of it is due to manufacturing having moved to the Pac Rim. In addition, many design services, including design for test, are moving to India.
Q. Is DFT remaining its own discipline, or is it blending in with other design functions?
A. These functions are blending together—that’s definitely something we see. And in addition to DFT, there are some new flavors that actually reinforce the blending. For example, design for debug is another flavor of activity that some consider part of design, and in fact they consider it one of the most expensive parts of design—to make sure the silicon works. In design for debug, hardware structures are introduced into the design that help in understanding in early phases of bring-up what is wrong. Then you have DFT—including scan, compression, and BIST as well as technologies for analog and mixed-signal circuits. In all these areas, a lot of infrastructure is added to increase observability into a device. Some of this infrastructure is used to bring up new devices, some for manufacturing test, and some for yield improvement.
Q. Is the increased participation from Asia due to the fact ITC, traditionally an east coast show, is now six hours closer to Asia, or is it mostly due to changing trends?
A. It’s my thinking that it is mostly due to changes in the industry. As I mentioned, more manufacturing is done in foundries in Asia as business models change and as more semiconductor companies go fabless. And because test is very closely related to manufacturing, it’s not surprising that we are seeing an increasing number of ITC submissions from these areas. We in the program committee are still analyzing this trend and trying to better understand it and better serve the test community as it evolves.
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