Meeting PCIe 2.0 physical- and protocol-layer test challenges
Rick Nelson, Chief Editor -- Test & Measurement World, 10/1/2007
| What does GT/s mean, anyway? |
| View “Successfully negotiating the PCI Express super highway towards full compliance.” |
Topics that Eads focuses on include de-embedding your test fixture, which, he reports, you must do when making measurements at 5 GT/s. De-embedding, he says, is the process of deconvolving the effects of your compliance test board to yield an effective measurement at a DUT's transmit pins. He cites the advantages and disadvantages of various methods, ranging from S-parameter de-embedding to time-domain gating (figure).
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Various methods of fixture de-embedding involve tradeoffs between accuracy and ease of implementation. |
Gordon Getty, an application engineer at Agilent's logic and protocol test group, concludes the 1-hr Webcast with a description of protocol test requirements, covering topics such as Config Space testing using the PCIECV tool provided by the PCI Special Interest Group (PCISIG, www.pci-sig.com). He covers link layer tests (a cross section of tests that, if the device passes them, would indicate a reasonable chance of interoperability) and transaction layer testing (which includes checking advanced error reporting capabilities). He also covers LTSSM (Link Training and Status State Machine) and ASPM (Active State Power Management); the latter is used to reduce power consumption in PCIe devices.
View “Successfully negotiating the PCI Express super highway towards full compliance” sponsored by Agilent, EDN, and Test & Measurement World and presented live August 29, 2007.
