Phase steps overcome slim testing margins

With many circuits and systems using clocks faster than 1 GHz, common-phase jitter, drift, and clock skew can affect measurements such as setup-and-hold times. Automated test equipment (ATE) typically strobes clock and data signals with a single strobe with fixed timing that cannot accommodate dynamic phase shifting. To remedy this inadequacy, you can employ a technique that applies a series of strobes—each slightly shifted in phase relative to clocks and data—to accurately test and characterize signals in I/O interfaces such as DDR-SDRAM.

As signal propagation along on-chip interconnects became a limiting factor in device speeds, circuit designers turned to source-synchronous interfaces to alleviate long clock runs. Source-synchronous interfaces receive a master clock and create a local clock for nearby circuits. Local clocks reduce problems caused by power-supply peaks, power and ground noise, local thermal heating, and electromagnetic interference (EMI).

Figure 1. In the presence of only static skew to the reference clock, the phase of output clock and data transitions is stable over time.

Shifts in a signal’s phase can change the circuit timing relative to the ATE, a factor you must keep in mind when testing a source-synchronous interface above 1 Gbps. (“Source-synchronous interfaces,” explains how the interfaces work.)

Static skew between a local clock and the system clock isn’t a difficult problem to overcome. You can use a test method called “output dependent timing” to measure setup-and-hold times. With this method, the test system determines the phase of the transitions in the clock and in the data signals and then sweeps a compare strobe across the timing signals while it monitors the error count. The tester then assigns the correct compare-strobe timing that it keeps for the remaining tests of the device. The phase of the transitions should be stable from bit to bit and shouldn’t contain excessive drift or jitter.

Figure 1 shows that for conditions of skew only, the phase of transitions between a reference clock and a source-synchronous circuit’s clock remains constant. Thus, an ATE system, which provides the reference clock to the device under test (DUT) during test, can measure setup-and-hold times with a fixed strobe with constant phase relative to the output clock and data.

Figure 2. In the presence of dynamic common-phase drift and jitter, the phase of output clock and data transitions with respect to the reference clock changes over time, reducing the chance of accurate measurements of setup-and-hold time with a fixed ATE strobing point.

But common-phase drift and jitter will affect measurements if you use a fixed-phase strobe, because when the amplitude of the common-phase jitter is large enough, the moving transitions consume the entire margin, causing failures as soon as the transitions cross the fixed strobe positions. The common-phase drift and jitter cause a data eye to close more than in the device’s real application. Therefore, you can’t determine parametric (setup time or hold time) data related to the dynamically changing phase of the source-synchronous clock.

Figure 3 highlights the impact of the common-phase jitter. To illustrate the problem, we’ve rotated the bits counterclockwise by 90° so you can see how the phase of the transition points changes over time. The data’s transition points and clock edges track the sine wave that represents jitter amplitude and shape. When the jitter is minimal, the transition points and clock edges will still align with the ATE system’s fixed-phase strobe (left-pointing arrows), but timing violations will occur in some bits (indicated by lightning bolts) because of drift and jitter.

To address the timing problem, we’ve developed a software-based method for testing source-synchronous interfaces even when the common phase shows dynamic variations in drift and jitter. The method is based on traditional “capture and compare” pin electronics. It scales with the available hardware, and you can easily adapt it for your application.

Figure 3. Data crossover points and clock edges varying in time because of jitter may not occur at the proper time to be correctly captured by a tester with a fixed timing strobe.   Figure 4. Multiple fixed strobes let you find the strobe phase locations that produce valid measurements of setup-and-hold time.

In Figure 4, the cycle N–1 yields a pass for strobe settings 2 through 5 on the data-bit line and for strobe settings 1 through 3 on the clock line. Phase steps 2 and 3, where both data and clock lines pass, represent valid test setups. The error-free phase margin for cycle N–1 is one phase step.

For the technique to work, the pattern must repeat and the step width between strobes must be small enough for the ATE to find the required points. Even if the distortion varies from one test execution to another, the specified criterion is still valid. You can accept a cycle as passed if it passes with at least one strobe. Because different cycles can pass in different shots, you can accept the whole pattern if every cycle passes in at least one shot.

Unlike characterization testing, production testing typically doesn’t include measurement values. Instead, it uses “pass/fail” testing. The test time for a setup-and-hold time pass/fail verification using our suggested algorithm includes multiple-pattern execution and loading and post-processing of the error data. For cases with long patterns and wide search ranges, the resulting test times are too long for production. To achieve an acceptable test throughput, you need a certain level of ATE hardware support.

You should focus on a few key areas to optimize for high-volume throughput. First, you need the ability to acquire error information per bit at full speed as well as the ability to acquire large amounts of error information within a pattern run. You must also minimize the amount of data that you need to upload and process.

The Verigy V93000 tester-pin electronics that we used to implement the test method let us perform Boolean operations on the strobe results of the data and clock pins per cycle during upload. This reduced the amount of upload data that finally passed the serial link between the tester and the controller by a factor proportional to the sum of data and clock pins per source-synchronous domain.

An additional option is to avoid the data upload altogether and perform the data processing within the tester hardware, so that just the global pass/fail test results need to be communicated to the tester controller. Performing the postprocessing directly in the hardware eliminates the need to upload massive strobe result data and improves throughput by several orders of magnitude.

Figure 5. Data processed in hardware results in shorter test times.

Designed for use with standard ATE, the test methodology we’ve described is based on traditional capture-and-compare pin electronics. You can scale the technique with your ATE hardware. The test method lets you perform both measurement (characterization) and validation (pass/fail) of timing parameters with fast throughput. You can also perform detailed analysis of failure mechanisms, including waveform shape, amplitude, and spectral content of common-phase drift and jitter.