Magma unveils Talus ATPG and Talus ATPG-X, partners with Inovys and Source III
-- Test & Measurement World, 10/15/2007 6:28:00 AM
Magma Design Automation has unveiled its Talus ATPG and Talus ATPG-X with on-chip compression. The company also announced it has partnered with Inovys to ensure interoperability of Magma’s Talus ATPG and Talus ATPG-X with Inovys’s Ocelot tester. Magma has also collaborated with Source III to offer a direct path from Talus ATPG and Talus ATPG-X to variety of a test programs.
Designed to concurrently target multiple fault models, the multithreaded Talus ATPG is fully integrated into Magma's Talus IC implementation system and leverages the unified data model architecture to access timing, layout, power, and other design data. Talus ATPG, for example, can generate tests for subtle bridge defects and crosstalk. Access to Magma’s unified data model allows Talus ATPG to support current fault-models and scale to support future models. Talus ATPG-X includes on-chip compression, offering a 40X reduction in test data volume. Talus ATPG also diagnoses tester failures to find the logic and physical location of the defect. Diagnostic results can be passed on to Magma's Knights Camelot and LogicMap products for correlation and failure analysis with the physical and electrical defects uploaded from the Magma Knights YieldManager product.
"As designs move to smaller geometries, we must handle new, complex defect mechanisms. Generating test patterns with traditional ATPG tools becomes more complicated and time consuming," said Camille Kokozaki, director, design automation services of IDT. "We find Magma's seamless flow and tight integration of ATPG, timing and physical layout to be very compelling."
"As a recognized innovator in communications technology, we are always looking for technologies to help us be first to market," said Jeff Hannon, VP of Engineering at Comtech AHA. "With Talus ATPG's multi-threaded engine, pattern optimization techniques, and ability to target multiple fault models in parallel we can generate more effective test patterns faster, helping us reduce turnaround time and costs on our advanced ICs."
"With the increasing cost to design and manufacture ICs, making the test process more efficient is critical—if you can't test it, don't build it," said Kam Kittrell, general manager of Magma's Design Implementation Business Unit. "The addition of Talus ATPG greater strengthens the Talus platform's test capabilities, allowing our customers to have higher confidence in their ability to build, test and profit from their IC designs."
Inovys, Source III agreements
Magma also announced it has partnered with Inovys to ensure interoperability of Magma’s Talus ATPG and Talus ATPG-X with Inovys’s Ocelot tester. Magma has also collaborated with Source III to offer a direct path from Talus ATPG and Talus ATPG-X to variety of a test programs.
Magma and its partners are also developing validated feedback paths from testers to the diagnostic capability in Talus ATPG that will allow designers to further analyze the causes of device failure. With a foundation in the IEEE 1450 Standard Test Interface Language (STIL) and through its collaboration with Inovys and Source III, Magma reports it is working to improve test quality, streamline the test flow and reduce test costs.
"For over 20 years Source III has been developing CAE tools that aid designers in the data-intensive aspects of design, simulation and test," said John Cosley, CEO of Source III. "We're pleased to further our efforts by working with Magma to offer a direct path from Talus ATPG to test programs for a wide variety of automatic test equipment (ATE)."
"Recognizing that test is more than patterns generated by EDA tools, Magma continues to broaden its product portfolio to better address the design and test challenges of nanometer ICs," said Magma’s Kittrell. "We are also committed to partnering with other test technology leaders. Delivering interoperability with leading test providers' products is a significant milestone in Magma's DFT product roadmap and ensures that our products work with our mutual customers' test equipment."
Magma will be highlighting Talus ATPG and Talus ATPG-X at the International Test Conference October 23-25 in Santa Clara. Demonstrations of the new products as well as the interoperability with the Inovys Ocelot test systems will be available in booth 320.
"Inovys is pleased to be working with the top EDA providers to provide a seamless path between design and test that enables semiconductor companies to reduce design debug from weeks to hours and accelerate time to production with unique failure analysis tools," said Colin Ritchie, VP of marketing at Inovys. "Ensuring interoperability of Talus ATPG with our family of Ocelot test systems enables our mutual customers to further reduce the development and test costs of their advanced ICs."
Magma is also sponsoring a luncheon at ITC, Oct. 23 at 11 a.m. featuring Dr. Mohammad Tehranipoor, assistant professor in the Electrical and Computer Engineering Department at the University of Connecticut. Dr. Tehranipoor will discuss the need to bring layout, timing and variation information into DFT/ATPG.
www.inovys.com
www.magma-da.com
www.sourceiii.com
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