A test transformation (Guest commentary)
William Mann, General Chair Emeritus, IEEE Semiconductor Wafer Test Workshop -- Test & Measurement World, 10/15/2007 8:52:00 AM
Editor’s note: This article is part 1 of a three-part series.
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The increasing complexity of semiconductor devices certainly hasn't helped the cost of test issue. In the brute force, number crunching world of microprocessors, internal speed and the number of transistors per chip have increased from one to two orders of magnitude in the past ten years. The May 1997 Pentium II ran at 300 MHz and had about 10 million transistors, whereas the June 2006 Dual Core Itanium 2 runs at 1.6 GHz and has over a billion transistors. The more application specific devices have undergone similar size and performance increases with completely integrated systems on a chip (SOC) and multiple devices in systems in a package (SIP).
Memory devices have experienced the most dramatic increases. The number of bits per device has skyrocketed, and stacked memory chips further complicate the testing problems. Digital cameras and portable media players created new NAND flash memories with gigabits of storage per device. Larger and more complicated redundancy repair methods, a variety of design for test (DFT) and built in self test (BIST) features, tunable threshold sense amps, multiple bits per cell, and a demand for massively parallel testing have also further complicated the testing challenge.
ATE cost reduction
By the late 1990s, the need for a $5 million, general-purpose, automatic test equipment (ATE) was apparent. The user rebellion against the constantly increasing cost was obvious. ATE suppliers initially addressed the problem with a variety of new product releases. Scaled down, limited performance versions of their high-end testers were offered, and add-on modules such as RF instruments within or on top of the test head became available to extend the capabilities of existing platforms. Lower cost specialized or dedicated test platforms were designed for particular high-volume products like power devices, image sensors, and LCD drivers (3.7 billion units in 2006!). In 2003, ATE suppliers began providing new tester architectures taking advantage of the scan design-for-test features incorporated in most of the designs. This new generation of "DFT testers" didn't provide hundreds of high-speed pin electronics and timing generators, so they were dramatically less expensive than their general-purpose predecessors.
The next step towards cost-reduced ATE was to standardize the interfaces (both software and hardware), and extend the equipment lifetime by providing an "open architecture." Tester suppliers promised that new test instruments, not even feasible at the time of the initial platform release, would become available as time and technology advanced. NP Test (now part of Credence Systems) and Advantest promised that third parties could develop "plug-and-play" instruments for their Sapphire and T2000 new platforms; LTX and Teradyne said they would enable and integrate such instrument into their existing Fusion and Flex platforms; and Verigy said its 93K platform was "the last platform anyone would ever need," implying they would design new instruments as the need developed. Even though the open-architecture concept might not significantly reduce the initial capital investment, the concept of extending ATE platform life offered reduced depreciation, or the cost per year of ATE ownership.
Test is being transformed
In spite of reductions in some ATE costs, a dramatic test transformation was necessary. The trend towards DFT used to reduce or at least contain the ATE requirements has been effective and it will continue. Evolutionary and incremental cost reductions are necessary, but they alone are not sufficient to achieve the significant overall test cost reductions desired. IC manufacturers realized they couldn't simply meet their goals by demanding lower cost equipment, while at the same time requiring improved performance. There had to be new strategies in IC testing. There are now fundamental changes, or test transformations taking place within IC test technology.
This article is part 1 of a three-part series. Continue to part 2, “Parallel testing,” or part 3, "Scotty, more power."
William Mann is the founder and served 16 years as the General Chair of the IEEE Semiconductor Wafer Test Workshop. He has served on the International Test Conference Program Committee and is on the Advisory Board of Design and Test of Computers magazine. He can be contacted at william.mann@ieee.org.
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