ITC: Keynoter addresses challenges of nanotechnology and giga-complexity
-- Test & Measurement World, 10/24/2007 10:06:00 AM
Santa Clara, CA. For more than half a century—ever since the Eniac debuted in the 1940s—computing performance per unit weight or per unit volume has increased two orders of magnitude every 10 years. That’s a fact that Gadi Singer, VP and GM of Intel’s mobility group, related to attendees of this year’s International Test Conference in his keynote address, titled “Meeting the challenges at the extreme ends of the spectrum—nanotechnology and giga-complexity.”
But such smooth growth in performance, he said, does not indicate smooth transitions in every aspect leading to that performance increase. He likened what’s happened in the electronics industry to what’s happened in manned flight—improvements could not have continued had the hot-air balloon not given way to the jet engine. In general, he said, smooth, exponential growth is usually accompanied by discontinuities and inflection points. And now, he said, as process geometries shrink to 65 and 45 nm, VLSI test and validation technologies and practices have reached the point where discontinuities or inflection points will be necessary for progress to continue.
Singer suggested that the changing nature of IC markets is driving these trends. To date, he said, PCs have been noted for being smart and flexible, while consumer-electronics devices have been noted for their mobility and simplicity. That, he said, is changing, as what he called the “Internet effect”—the convergence of rich experience affecting all devices—is driving mobile devices to become as smart and flexible as PCs have been. The two-orders-of-magnitude every-ten-years effect, he said, could enable a wristwatch PC by 2015.
Key drivers, he said, are CPUs having multiple heterogeneous programmable dual- and quad-cores and that combine complex video and graphics subsystems as well as high-bandwidth I/O and multiple communications interfaces. He cited as an example Intel’s nest-generation 45-nm NEHALEM, which will have 700M transistors and up to eight cores with two threads per core and which will allow power to be managed dynamically on demand.
Such devices will change the nature of test, he said. Scan test will not be able to detect subtle speed-related failures, and no automated solutions are available for functional core test.
He cited four distinct trends that he said will affect test. First is increasing complexity and diversity, which is occurring because of the extreme modularity associated with embedded IP blocks. The complexity and diversity in turn will require that test—for digital, analog, and RF circuitry—be accounted for in the design process.
The second trend, he said, is the move to high performance and low power. Consumers want more functionality in smaller form factors with extended battery life. Consequently, the past solution to increased functionality—more performance at the cost of higher power consumption—will no longer suffice. To do that, supply voltages are falling, but that in turn introduces test challenges because of anomalous Fmax behavior at low Vdd levels. Consequently, test must take place at various environmental conditions, and at-speed power testing and at-workload power testing will be essential.
The third trend, he said, is the emergence of nanometer devices. Moore’s law alive and well, he added, as technology innovations continue to sustain it. But those innovations—which are discontinuous—present test challenges related to copper+low k, strained-silicon, high-k-plus-metal-gate fabrication technologies.
The final trend, he said, is the continuing reduction in design turnaround time. End products, he said, are refreshing at a rate of twice per year. What’s needed to cope, he said, are clear metrics and turnaround-time (TAT) goals for each stage from development through prototyping to production. The test community, he added, must keep up with the design community in developing procedures to measure TAT.
He concluded that the combination of trends will require a new approached to test, involving up-front design considerations, extreme modularity to enable test manageability, TAT metrics, and the creation of adaptive, self-adjusting test techniques.
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