ITC: Chipmakers employ Cadence test technology
-- Test & Measurement World, 10/30/2007 5:47:00 AM
Representatives of Cadence Design Systems were on hand at the International Test Conference to report that companies including K-micro, LSI, G2 Microsystems, and IBM have made use of Cadence’s timing-aware, power-aware, and small-delay-defect tools.
The company noted that its technology has helped companies including Kawasaki Microelectronics (K-micro) and LSI to cost-effectively produce large numbers of high-performance, high-quality, super-dense integrated circuits by making use of Encounter Test test-generation and compression technology.
Cadence said it has developed Encounter True-Time Test ATPG, which generates accelerated tests to rigorously exercise a design using on-product clock generation (OPCG) and faster-than-at-speed tests to find and eliminate small delay defects that might otherwise go undetected using traditional transition testing. Encounter True-Time Test ATPG also features timing-aware vector generation that uses SDF data to create vectors that are right by construction, as opposed to alternative solutions that do not use actual circuit timing. This results in more accurate vectors and fewer false failures, eliminating the need for time-consuming iterative debug and refinement to arrive at a good set of vectors.
Cadence was able to demonstrate Encounter Test compression technology and Encounter True-Time Test ATPG on a DSP processor design at LSI. The Encounter True-Time Test ATPG was able to generate effective test patterns to meet the quality needs of the LSI design team and improved defect containment within a fixed test data volume budget. "Through the Cadence Encounter Test compression technology, and Encounter True-Time Test ATPG, we were able to meet our test data volume requirements with a highly effective set of tests," said Rick Muscavage, technical manager for DSP IC design at LSI. "Our requirements were tough, including some very challenging scan structures not typically supported by other compression structures, but the expert Encounter Test support team came through for us."
Similarly, Cadence reported, Encounter Test allowed K-micro to embark on an advanced SOC design with significant amounts of embedded memory and multiple clock domains. To meet this challenge, and to improve the overall quality of their chip, K-micro deployed Encounter True-Time Test and heavily leveraged OPCG and test compression to successfully improve overall product quality. "Encounter Test provides the capabilities K-micro requires to address design and test requirements for large, complex SOC products," said Yoshito Muraishi, director of CAD development for Kawasaki Microelectronics. "Encounter True-Time Test ATPG achieved our stringent quality requirements for delay testing, and the compression structures allowed us to eliminate x-states caused by aggressive use of delay testing and still have a cost-effective test program."
"Cadence Encounter Test compression technology and Encounter True-Time Test ATPG are proven technologies for testing advanced semiconductor designs," said Sanjiv Taneja, VP of Encounter Test R&D at Cadence. "This is a key combination to ensure highest quality while minimizing test cost for nanometer designs."
IBM, G2 adopt Cadence tools
Cadence also said that it has helped IBM deliver high-quality, high-volume chips for consumer devices by enabling the detection and correction of small delay defects—miniscule defects that are nearly invisible without sophisticated test programs that operate above the normal operating speed of the chip. Most recently, the Cadence Encounter Test solution was able to help IBM meet its goals for quality and volume production of a high-performance custom chip based on IBM's Power Architecture technology.
"The Cadence Encounter Test team has a capability called small delay defect detection," said Ron Martino, director of Power Architecture, IBM Global Engineering Solutions. "What this means is, they can detect a timing delay in a signal that is caused not by a broken wire, but by one that is merely a few atoms thinner than it is supposed to be. The difference in thickness creates a difference in resistivity, which delays the signal for a fraction of a nanosecond. In many high-performance, high volume applications, that's just too long."
"By using the Encounter True-Time Test capability, IBM was able to assure low defect rates for a superscalar chip design," said Sanjiv Taneja, vice president of Encounter Test R&D at Cadence. "This was important for IBM, it's important for their customer, but most of all, it's important for users of high-performance systems, because it demonstrates that there are ways to enable higher quality even as the semiconductor industry moves to smaller and more complex technologies."
Finally, Cadence announced that G2 Microsystems has developed wireless mobile tracking devices using the Cadence Low-Power Solution. This complete, integrated flow, based on the Si2 standard Common Power Format (CPF), enabled G2 Microsystems to achieve faster time-to-market and ultra low-power objectives. Said Andrew Adams, VP of IC design at G2 Microsystems, "We looked for strong low-power design tools together with integration of the design flow to ensure the fastest possible time-to-market. Our evaluation led us, conclusively, to the Cadence Low-Power Solution." Using the Cadence integrated environment, G2 engineers were able to meet the stringent power requirements for their latest design while also ensuring product quality through very high test coverage.
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