Test cocktail reaching its limit?

E-mail

Traditional test approaches are failing to keep pace with the requirements of dense, complex devices, according to comments from participants in the 9th European Manufacturing Test Conference (EMTC), held October 9 in Stuttgart, Germany, in conjunction with Semicon Europa. Conference chair Rene Segers of NXP Semi-conductors kicked off the day-long event by noting that the traditional digital test cocktail, consisting of ATPG plus delay and I_DDQ tests, is running out of steam. Further, he said, analog test remains an art that resists structural-test approaches.

During the conference, engineers representing both test vendors and semiconductor makers described efforts to extend test to meet today’s needs. Software will have a key role to play, according to keynote speaker Dan Glotter, CEO of OptimalTest. He proposed that enterprise test-management software can improve yield by 1 to 4% (by reclaiming false fails) and reduce DPPM levels by 20 to 50%. But software alone won’t solve all the challenges, and additional presenters described other approaches for improving test processes:

• Stephane Mougin, a product engineering manager at STMicroelectronics, described the application of a Credence Sapphire test system in a multiple-time-domain approach to improving test quality while reducing test cost.
• Enrique De Guzman, a test engineer at AMI Semiconductor Philippines, discussed the impact of test-handler temperature characteristics when testing temperature-sensitive devices. He concluded that the optimization of handler soak time can improve both yield and test capacity.
• Peter Hotz, a field product specialist for RF test at Teradyne, described the use of field solvers and evaluation PCBs for developing best practices for RF device-interface-board layout.
• Joachim Moerbt, department manager responsible for mechatronics activities at < ahref="http://www.advantest.de/dasat/"> Advantest Europe, described a flexible high-parallel device interface for testing DRAM modules at 400 MHz.
• Jerry Broz, senior applications engineer at International Test Solutions, described off-line methodologies for assessing online wafer-probe contact-resistance performance to optimize cleaning protocols.

Finally, Ajay Khoche, lead consultant for advanced test methodologies at Verigy—recognizing that faults will never completely go away—described efforts toward using the Standard Test Data Format (STDF) to streamline test-failure dataflow to enhance volume diagnostics.

The ultimate lesson of the workshop seems to be that no one solution will suffice to contend with all DUT fault mechanisms. Test vendors and their customers will need to collaborate to enhance existing test cocktails while developing new test techniques.