Tools take aim at memory yield

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Yield ramping is becoming a critical aspect of chip design and production as geometries shrink to 65 nm and below. The topic garnered widespread coverage at last month’s International Test Conference (October 21–26, Santa Clara, CA).

As Janusz Rajski, ITC program chair and Mentor Graphics chief scientist and director of DFT engineering, put it in an interview before the show, “We have noticed that a lot of the challenges we saw in the past are compounding when we go to 65 nm and below. Issues related to power and to the staggering complexity and small feature sizes of 65-nm devices add new types of defects—including systematic defects—that can impact yield.”

Many presentations and product highlights focused on yield enhancement for system-on-chip (SOC) devices. But of course, yield has long been an issue for memory chips as well. As Dr. Yervant Zorian, Virage Logic’s VP and chief scientist, puts it, “Memories are defect magnets,” attracting random, systematic, and parametric defects.

To help deal with such defects, Virage at ITC introduced a new version of its Self Test and Repair (STAR) memory system. Originally introduced in 2001 and, according to Zorian, now employed by more than 100 companies, STAR has gained a dashboard of user-selectable options that let users make tradeoffs between test time, die area, and diagnostic resolution.

The STAR system from Virage Logic includes manufacturing-automation components, which complement the technology’s design-automation and silicon-IP features.

The goals, said Zorian, are to localize a defect to a specific cell, to determine whether the cause is design- or process-related, and to learn from current chips to improve future ones. Project-based pricing for STAR with Yield Accelerator begins at $50,000.

Virage Logic also announced that it has opened the STAR memory system architecture to enable the integration of commercially and internally developed memories. Brani Buric, VP of product marketing and strategic foundry relationships, said the intention is to unlock the technology’s value for customers whether or not they use Virage Logic memories.

In addition, Virage announced the availability of a new family of 65-nm products: SiWare Memory compilers and SiWare Logic libraries. SiWare Memory includes a portfolio of silicon-aware, power-optimized, 65-nm memory compilers along with a dashboard capability for managing design tradeoffs; SiWare Logic includes yield-optimized standard cells, multiple-threshold process variants, engineering change-order kits, and ultralow power kits.

The new offerings broaden the company’s Silicon Aware IP portfolio to enable customers to design faster, lower-power, and more area-efficient SOCs while achieving higher yields. Project pricing starts at $70,000.