ITC: Talus ATPG touted, test issues cited at Magma event
Rick Nelson, Chief Editor -- Test & Measurement World, 10/31/2007 7:51:00 AM
Magma Design Automation highlighted its new Talus ATPG and Talus ATPG-X (the latter adds on-chip compression) at the International Test Conference.
At a Magma-sponsored October 23 lunch presentation, Dr. Mohammad Tehranipoor, Assistant Professor in the Electrical and Computer Engineering Department of the University of Connecticut, said that engineers can expect to see more interconnects and more vias, making interconnect delay a dominant characteristic, along with bridging defects and defects related to opens and missing vias. SSA fault models will no longer suffice, he said, and engineers need more advanced fault models as gross delay defects give way to small delay defects.
He questioned the capabilities of traditional ATPG: Does it understand power-supply noise (which adds an Ldi/dt component to IR drop), temperature effects, and crosstalk? Is it layout-aware? Does it allow you to use test data to help with diagnostics and boost yield? Effective tools for which the answer to these is “yes” will require access to a large database, he said, such as the one associated with Magma’s unified data model.
In a follow-up address, Magma software architect Rob Thompson asked whether your ATPG could see the types of defects occurring today: “If it’s reading a Verilog netlist, chances are it can’t,” because today’s defects are found in the layout and timing domains. “If you can’t see defects,” he added, “you have to create lost of patterns and hope some of them work.” Then, he said, you face the problem of whether you are over testing. Talus ATPG, he concluded, assures access to all of your design, not just some of it, and it provides for a simple flow for all the fault models you want to consider.
Also speaking was Brad Lindstrom of Comtech AHA, a fabless semiconductor company involved in satellite communications systems. His test concerns going forward, he said, relate to quality, cost, and flow. With respect to quality, he said, he currently uses SSA fault models, is reviewing the effectiveness of Iddq and functional test, and is implementing delay and other fault models. With respect to cost, he said, he is now using on-chip output compression and is looking at an on-chip compression solution. Also, he noted that he wants ATPG to work effortlessly within his existing flow.
He said he experimented with Magma ATPG and found it yielded SAA test coverage similar to that of other tools; he added that the Magma pattern reordering (which puts the most effective patterns first) worked effectively with multiple fault models. Patterns, he said, were easy to generate, and he noted that Magma’s ATPG is multithreaded and therefore automatically runs on multiple CPUs. Going forward, he said he plans to experiment with on-chip scan-compression hardware and conduct delay and bridge fault experiments on his ATE.
Magma CEO Rajeev Madhavan concluded the presentation by emphasizing what he said was Magma’s commitment to addressing logical and physical issues together. That’s necessary, he said to handle multicorner variations, preventing a fix at one process corner from causing trouble at another. He also cited benefits of multithreaded tools: “It’s a multicore world. We are not going to get faster clocks going forward.” Finally, he concluded, “We envision a flow where test objects inserted at RTL level.”
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