The need for new ATE interface standards (Guest commentary)
Klaus Luther, Infineon Technologies -- Test & Measurement World, 11/21/2007 5:42:00 AM
The semiconductor market shift from business-enterprise to consumer-driven has been well documented. The associated decreasing average selling prices (ASPs), steep production ramp-ups, shorter product life cycles, uncertain volume forecasts, and impending rush to get ready for the next-generation “killer application” has become part of the integrated circuit (IC) manufacturer’s everyday’s life. These disparate forces often converge on the semiconductor test floor, which is the last major gate before product is shipped to awaiting customers and revenue is recognized. The substantial need for cost and operating efficiencies gained through standardization has never been greater and is continuously increasing.
While efforts have been underway over the past few years to drive the automated test equipment (ATE) industry toward standardization, these activities have only attempted to resolve some of the cost and efficiency issues associated with the total cost of semiconductor testing. ATE capital cost typically accounts for approximately 25 to 30 percent of the total cost of test. While this is a significant percentage of the overall test cost and rightly deserves to be closely scrutinized, tangible value can be realized through open, pre-competitive collaboration in the peripheral areas around ATE.
Many of these peripheral areas—including hardware docking for wafer probers and device handlers, data and program portability, and electronic design automation (EDA) software tools—are equally critical to test. Unfortunately, like ATE, the vast majority of the peripheral hardware and software is also proprietary in nature, which means that each requires a unique interface. This creates inefficiencies and additional costs for both end users and vendors alike. To support 16 ATE platform types as well as three wafer-prober and device-handler types, Infineon requires 40 different interfaces. Other semiconductor manufacturers must cope with a even higher number of interfaces. Clearly some significant level of standardization is required.
To better serve the dynamic and fickle consumer-driven market, integrated device manufacturers (IDMs) like Infineon have adapted their manufacturing processes to be more responsive to unpredictable volume product ramp-ups and the associated downward ASP pressures. With greater frequency, this supply chain must include and take advantage of wafer foundries and outsourced semiconductor assembly and test (OSAT) service providers. This general outsourcing trend adds another layer of complexity to the manufacturing process and further underscores the need for standardized peripheral interfaces.
With standardized interfaces, IDMs and OSATs can greatly diminish test-floor complexity by minimizing the number of unique interfaces and their associated spares inventories. Initial capital and recurring costs are significantly reduced, test-cell qualification and correlation costs are eliminated or curtailed, and production downtime is optimized by minimizing shop-floor variability caused by set-up, change-over, and troubleshooting time. This results in higher equipment utilization and greater throughput, which directly lowers the total cost of test. The manufacturing line is easier to balance and becomes more flexible to better meet ever-changing and last-minute production demands, especially at critical end-of-quarter crunch times.
Equipment suppliers also benefit from standardized interfaces by reducing the need for redundant R&D expenses for developing non-differentiating, yet required features from scratch with every product generation. Manufacturing economies of scale can be gained by producing higher volumes of a few standardized interfaces that correspond to and fulfill demanding market requirements, as opposed to producing lower volumes of multiple proprietary interfaces. Similar to the IDMs and OSATs, suppliers can also see substantial savings in reduced inventories and recurring costs. Reducing the variety of available options also helps to avoid misunderstandings and misinterpretation between various standards and nomenclatures.
IDM’s continually improve their supply chain processes, but over the years incremental gains have become harder to achieve. Clearly an individual IDM can accomplish only so much on a global basis. Yet, consumers continue to demand greater content and features in their products, at lower prices—so what else can be done? There is an urgent need for an industry-wide solution that leverages the best practices in a pre-competitive environment.
The Semiconductor Test Consortium (STC) recently launched its Semiconductor Test Interface eXtensions (STIX) initiative, which addresses the peripheral areas around the ATE. Within the STIX initiative, ATE is treated as a non-architecture-specific “black box.” At the core of this industry-wide effort is an ecosystem of suppliers and users working collaboratively to develop and implement these critically needed ATE interface standards. Working groups have already been formed to address areas including industrialization of Semiconductor Test Interface Language (STIL) and the establishment of docking and interface and probe-card interfaces. Future areas of interest include a user-level application programming interface (API) to provide a common user programming interface across tester platforms, portable test instrument modules (PTIM) for low-cost integration of ancillary instruments across legacy tester platforms, and a tooling abstraction layer for common components required for the interconnect from test instruments to the tester performance board.
Standardization of ATE interfaces creates economies of scale that is beneficial throughout the complete supply chain. This allows both end users and vendors to focus on and leverage their core competencies to the fullest extent by reducing redundant R&D and lowering manufacturing and infrastructure costs in areas that do not differentiate their products. Also the ability to massively decrease lead time should not be forgotten—this specific need continuously becomes a very important requirement. ATE suppliers who can fulfill very short lead times have a major competitive advantage. By working collaboratively within the industry on new ATE interface standards, overall efficiencies can be maximized and total cost of test can be minimized, which benefits the entire test community.
Klaus Luther holds a diploma degree in electrical engineering from the University of Dortmund. He is Vice President, Test Group, at Infineon Technologies. During his career he has held several positions in R&D and manufacturing and one international assignment at Infineon's Memory Assembly and Test Operations in Portugal. Klaus has been a member of the STC Board of Directors since April 2006.
Read related guest commentary, "Thinking out of the box: Expanding STC's impact with STIX," by Steve Wigley of ATE manufacturer LTX.
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