Increasing abstraction makes DFT more effective (Guest commentary)
Chouki Aktouf, DeFacTo Technologies -- Test & Measurement World, 12/7/2007 6:13:00 AM
According to the latest International Technology Roadmap for Semiconductors, the cost of manufacturing chips is approaching the cost of testing them. Chip quality is compromised in new deep submicron technologies because new defect types are appearing all the time. To cope with cost and quality, semiconductor manufacturers require increasing amounts of design-for-test (DFT) functionality, and this trend is only expected to continue. IC designers will continue to use mainstream DFT methods such as scan, test compression, and built-in self test (BIST), but they will also need new DFT solutions that ensure that design and test requirements can be met.
Although there is a consensus that higher levels of abstraction are required to manage increasing design complexity, DFT solutions are still stuck at the gate and physical levels. Such low-level DFT unduly burdens today’s design flows and methodologies because of the strong dependency on the heavy synthesis process.
Take, for example, traditional gate-level internal scan. It currently impedes any complete and cost-effective design verification and debug process for two reasons: one, because it comes late in the design flow; and two, because gate-level netlists with scan are tremendously complex and very difficult to debug at the gate level.
The idea of moving DFT to a higher level, particularly to the register-transfer level (RTL), is not new. The problem has always been one of providing acceptable Quality of Results (QoR)—that is, QoR comparable to traditional low-level approaches. QoR implies both quality and cost. Quality is related to DFT expectations such as test coverage. Cost relates to several parameters such as performance degradation, area overhead, and testing time.
RTL DFT, starting with mature DFT methods such as scan, will be widely adopted when proposed solutions demonstrate both quality and cost-effectiveness, and when they improve existing design flows without disrupting them. A typical RTL-to-RTL internal scan solution should allow both DFT rule checking and implementation of scan logic fully at RTL. This would mean straightforward simulation and debug capabilities of ATPG test patterns, which strengthen design sign-off capabilities, pre-synthesis. RTL-to-RTL scan would also positively impact current IP-based design methodologies. DFT analysis correction and scan implementation fully at RTL provide better quality, reusable IP. What’s more, IP integration will be easier when designers know that IP cores are truly “DFT ready.”
Novel DFT solutions have to cope efficiently with the challenges faced by both the manufacturing testing community and the design community. Designers expect a DFT solution such as internal scan to be non-intrusive, to help solve critical problems in design verification, and to fit seamlessly with the rest of their DFT methodologies such as test compression and BIST. Bringing DFT up a level of design abstraction, to RTL, is a significant step on the right direction.
Chouki Aktouf is president and CTO at DeFacTo Technologies. Prior to founding DeFacTo, he was an associate professor of computer science at the University of Grenoble, France, and leader of the dependability research group within the INPG (Institut National Polytechnique de Grenoble). He holds a PhD in electric engineering from INPG and did post-doctoral research in the electrical engineering department at University of Southern California in Los Angeles and Dalhousie University in Canada.
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