Encounter Test Architect GXL

Cadence Design Systems, www.cadence.com

Encounter Test Architect GXL can insert, synthesize, and validate a full-chip, low-power design-for-test (DFT) infrastructure. The software provides for scan insertion using Encounter RTL Compiler's global-synthesis technology. It supports memory built-in self-test (BIST) as well as the inclusion of top-level I/O test structures (including an IEEE 1149.1 boundary-scan controller) and the creation of on-chip compression, allowing a choice of either a multiple-input signature register (MISR) architecture or an exclusive-or (XOR)-based architecture.

Encounter Test Architect GXL automatically uses a designer's power-intent information within the Common Power Format (CPF) to compile and connect all low-power DFT structures into a complete full-chip low-power test infrastructure. In supporting power-aware test, the product employs advanced power-management techniques to limit power consumption during manufacturing test.