ITC innovations span RF hardware to test software

Virage Logic introduced a new version of its Self Test and Repair (STAR) memory system, which has gained a dashboard of options that let users make tradeoffs between test time, die area, and diagnostic resolution. OptimalTest demonstrated new features of its OptimalTest Test Management Solutions (OT-TMS) suite of software, including the OT-Reports and Outlier Management tools. OptimalTest also reported that it has sold its OT-TMS software to a European IDM in a multimillion-US-dollar annual licensing deal. DeFacTo Technologies announced a design-for-test (DFT) product that analyzes an RTL integrated-circuit design, creates appropriate RTL scan-test structures, and inserts them into the RTL design. The product, HiDFT-Scan, works within existing design flows and with industry-standard synthesis tools.

Cadence Design Systems reported that companies including K-micro, LSI, G2 Microsystems, and IBM have made use of Cadence’s timing-aware, power-aware, and small-delay-defect test tools. Synopsys announced availability of its TetraMAX small-delay-defect automatic test-pattern generator (ATPG), extended low-power-management capabilities within the Synopsys Galaxy environment, and a new Odyssey DFT yield-management module. Magma Design Automation highlighted its new Talus ATPG and Talus ATPG-X (which adds compression) tools. Designed to concurrently target multiple fault models, the multithreaded Talus ATPG is fully integrated into Magma’s Talus IC implementation system and leverages the unified data-model architecture to access timing, layout, power, and other design data.

Mentor Graphics highlighted its new TestKompress Xpress technology, which, compared with the original TestKompress product introduced in 2001, increases the achievable level of compression by providing a more efficient way to handle so-called “X-states”—the unknown states that can arise during manufacturing test. Goepel electronic demonstrated the upcoming release 4.4.1 of its software platform, System Cascon, which adds improvements in third-party ATE integration while offering improved tools for the automated handling of non-boundary-scan components and clusters.

Asset InterTech expanded ScanWorks’ embedded-instrument support to include signal-integrity-analysis applications that support Intel’s IBIST (interconnect built-in self-test) embedded instrumentation technology. Intellitech demonstrated its new PT100 Pro test platform for testing PCBs with processors based on ARM architectures (See more in our News Briefs). Teseda highlighted its new 512-channel V550 desktop validation and diagnostic platform and announced that Hamamatsu Photonics will adopt Teseda’s V-series hardware as an option in its semiconductor-device failure-analysis systems.

Representatives of Inovys were on hand to tout Sun Microsystems’ purchase of multiple Inovys Zero Foot Print (ZFP) test systems that have been coupled with Inovys SpeedScan for high-speed characterization of Sun’s UltraSPARC CMT CPUs. Micro Control Company exhibited its LC-1 logic burn-in with test system, which can accommodate other vendors’ boards that have sizes differing from the standard Micro Control burn-in board dimensions.

Advantest chose Test Week to announce its 2GDM 2-Gbps source-synchronous interface test module and its 12-GHz 12GWSGA wideband signal generator/analyzer module for its T2000 OpenStar platform. FormFactor announced a new family of wafer-probe cards designed to address the rising cost and technology challenges associated with testing wire-bond logic and system-on-chip (SOC) devices.