Achieving PCI Express physical-layer compliance

With the emergence of the PCI Express 2.0 specification, data-transfer rates doubled from 2.5 GT/s to 5.0 GT/s. To develop effective receiver and transmitter tests for this faster rate, you'll need an understanding of PCI Express specifications as well as knowledge of system architectures, receiver tolerance measurements, stress elements, and transmitter PLL response.

In the 1-hr Webcast “Pass PCI Express physical layer compliance testing the first time,” Bent Hessen-Schmidt, VP of business development at SyntheSys Research, covers these topics and describes trends in jitter compliance methodology.

Path length differences in this common-clock-architecture-based PCI Express design can contribute up to 12 ns of delay. Other factors that can degrade transmitter (Tx) and receiver (Rx) performance include dispersion resulting from low-cost circuit-board material, crosstalk, and reflections.

Schmidt ends by describing dual-port measurements and saying that test methods are evolving to favor the use of sampling instruments as PCI Express speeds move toward 8-GT/s, with the concomitant 20-GHz fifth-order harmonics.

The Webcast, sponsored by Test & Measurement World, EDN, and SyntheSys Research, was presented live December 11, 2007. You can view the archived Webcast, which provides detailed descriptions of practical jitter-measurement techniques.