Accelerate and simplify serial data testing

Serial data streams continue to increase in speed while error specifications tighten, which makes testing for jitter tolerance and bit-error rate (BER) ever more important. Several engineers have tackled the problem in different ways but with similar results—they have all cut test time and equipment costs.

David Andres, a design engineer at Marvell Semiconductor, developed a method for accelerated BER testing of serializer/deserializer (SerDes) receivers. Chung Wu, product definer at Maxim Integrated Products, uses eye templates to define SerDes receiver performance, and Christopher J. Loberg, senior market development manager at Tektronix, uses a waveform generator to create test signals.

Although some customers have requested that Andres test for BER down to 10–18 (less than one error for every 1018 bits), most customers require BER verification for every 1012 bits. At those error ratios, a full BER test at 2.5 Gbps can take 6 min, 40 s. To attain a 99% confidence level that a bit error wouldn't occur, Andres would need to run a BER test at least 100 times per device for a total test time of more than 11 hrs.

Because Andres typically tests as many as 50 individual devices—for new designs, designs that have changed, or designs that need spot checking—he needed to shorten the test time. By setting up a test that increases the probability that a bit error will occur, Andres can reduce test time to a few seconds per device. This accelerated testing gives him enough confidence that the device under test (DUT) will achieve acceptable BER performance.

To accelerate his testing, Andres adds a controlled amount of timing variation (jitter) to a data stream so the jitter overlaps with an eye-mask specification. In one application, he produces four edges inside the eye mask for every 127 bits using a 7-bit pseudorandom bit sequence (PRBS7). The added jitter produces enough timing violations to predict a receiver's performance. He also uses PRBS23, PRBS31, and other bit patterns.

Andres combines two techniques to add controlled jitter to serial data streams: oversampling and mixing. Oversampling involves using a pattern generator that is four times faster then the bit rate of interest. He uses a 10-Gbps pattern generator to build a 2.5-Gbps PCI Express (PCIe) Generation 1 data stream.

To make a stable 2.5-Gbps data stream from a 10-Gbps signal, Andres uses four consecutive 1's (or a single F in hex) to make a single 1 bit at 2.5 Gbps. A 0 bit at 2.5 Gbps is made of four consecutive 0 bits at 10 Gbps. He then shifts the edge timing to create jitter.

Figure 1.  Four consecutive bits of the same polarity produce a data stream at ¼ of the highest bit rate (top trace). Changing the timing of an edge changes jitter in 0.25 UI increments, producing early or late edges (bottom trace).

Figure 1 shows how Andres does it. The upper trace shows four bits (1010) at 2.5 Gbps with no jitter added (no edges shifted). At 10 Gbps, the pattern is represented by F0F0 hex. The lower trace is a series of four bits (1,0,0,1) at 2.5 Gbps, but the rising edge between the 0 bit and the following 1 bit occurs 0.25 UI early.

Listing 1.  Using this code, David Andres of Marvell Semiconductor develops a PRBS7 pattern.

Listing 1 shows code that Andres uses to develop a PRBS7 pattern. The four underlined digits in Pattern Data Line0002 represent bits that are shortened or lengthened by 0.25 UI. For example, the “8” represents a late falling edge of the preceding bit and the “E” represents an early falling edge of the following bit.

Figure 2.  Adding jitter to a data stream can force it into the limits at the corners of an eye mask. Courtesy of Marvell Semiconductor.

The cursors that mark the width of a closed eye in Figure 2 correspond to 39-ps time between bit edges and indicate eye closure. A histogram above the waveform indicates the distribution of the edge timing. The range of jitter covers about 53 ps, with the remaining 14 ps of jitter coming from data-dependent jitter (DDj) and random jitter (Rj). “I don't like random jitter because it's so difficult to quantify and debug,” said Andres. “Random jitter grows the longer you make measurements.”

Figure 3.  David Andres of Marvell Semiconductor uses this test setup to test SerDes receivers for BER in the presence of jitter.

The pattern generator's output, which contains the jittered data stream, feeds the DUT. A clock output triggers a sampling oscilloscope to capture the waveforms and produce eye diagrams. An error detector counts bit errors from the receiver DUT's output.

Andres uses his technique to evaluate receivers for timing variations. He deliberately introduces as little amplitude variation as possible because amplitude variation will also affect receiver performance.

Andres started with more test equipment than he now uses, but he found ways to simplify the test setup each time he needed to create a new system. “When I started working here, I was the only one who needed a 12-Gbps BER tester,” said Andres. “Now, there are 12 to 15 engineers who use them. At $150,000 each, that's a lot of money, so I look for ways to reduce the amount of test equipment we use in each setup.”

Andres uses a delay line that lets him reduce the cost of a system because he can use an RF signal source that lacks an FM modulator. A delay line typically costs a few hundred dollars, but an FM modulator adds about $10,000 to an RF signal source. He also said that he can modulate an RF signal with sine waves up to 80 MHz with a delay line as opposed to 20 MHz with an FM modulator. The bad side of the delay line is that the amount of delay variation is typically limited to a few hundred picoseconds, while FM can produce variation of tens of nanoseconds at lower frequencies. Thus, he will use an FM modulator when necessary.

To further reduce costs, Andres purchases used equipment whenever possible. He noted that some BER testers include an integrated delay line, so you may not need to purchase an external one.

His first test setup included an FR4 stripline between the pattern generator's output and the DUT. That adds loss to the signal. Andres eliminated the stripline in later test setups because bit errors caused by backplane loss are difficult to debug. In addition, Andres said that you need a different stripline for each data rate, which reduces the flexibility of a test setup and adds to the cost. He also eliminated a real-time oscilloscope but will use it when he needs to debug a design.

Chung Wu of Maxim Integrated Products also evaluates SerDes receivers for jitter performance. In a paper entitled “Eye-pattern templates help evaluate serializer/deserializer performance,” Wu describes how he measures bit errors versus timing variations (jitter) and amplitude. The paper provides test results—in tabular and eye-diagram form—that show how temperature and cable length affect the amount of jitter that a receiver will tolerate before producing bit errors.

To evaluate a receiver for jitter, Wu's test system generates a controlled sinusoidal jitter. The synthesizer sweeper (an RF signal source) FM modulates its RF signal by the sinusoidal output of the waveform generator. Wu adjusts the amplitude of the signal at the receiver.

Wu's paper explains the process he follows: “When signal swings are larger than an observed threshold, the deserializer performance is determined mainly by jitter. We then perform a series of tests on a 5-m cable at a serial-data rate of 660 Mbps, and determine the maximum jitter the deserializer can tolerate for each given level of signal amplitude.”

Wu sets the amplitude to 100 mV_p-p at 25°C but needs 200 mV_p-p for devices at 95°C. He then varies the jitter to find the greatest amount that produces no errors for 2 min.

Figure 4.  A test setup used by Chung Wu of Maxim Integrated products uses a synthesizer sweeper that generates a modulated clock signal for a bit analyzer.

Chris Loberg of Tektronix suggests that you can simplify serial tests by using an arbitrary waveform generator (AWG) to generate signals for tests of serial receivers. Loberg argues that a direct-synthesis AWG (with a sufficient sample rate) can replace the noise generator, sine wave generator, and pattern generator used in traditional test setups.

Figure 5.  Chris Loberg of Tektronix has found that an arbitrary waveform generator can reproduce a digital bit stream and add analog signal characteristics.

Loberg's paper, “Direct approach to signal generation promises simpler compliance measurements for serial receivers,” explains how to use an AWG to create the entire test signal—jitter and all. Loberg acknowledges that serial devices expect to see digital waveforms, but he says that the sample points in an AWG's memory “can define essentially any wave shape, including digital pulses.”

Figure 5 shows the test setup that can perform a Serial ATA compliance test. The oscilloscope is optional, but useful for troubleshooting.

These three applications demonstrate how you can accelerate BER tests, use eye masks to predict SerDes receiver performance, and simplify your test setup. Unless you are required by a standard to perform a test in a particular way, you have the freedom to improvise.