As SOCs grow, instruments move on-chip

As system-level ICs grow larger and more complex, they become impossible to observe and stimulate. Internal nodes aren't accessible to bonding pads or even to probes. Signal voltages are small, noise thresholds are tiny, and drive strengths are negligible. As critical circuits reach gigahertz frequencies, it becomes physically impossible to get an accurate representation of signals off the die, even if you can probe the circuit.

Yet, the need for capturing on-chip-signal information remains. Chip designers must be able to observe and stimulate individual blocks in a system-on-chip (SOC) to bring up the silicon. Manufacturing-test engineers must be able to create fast test programs on affordable test equipment. Increasingly, chip designers must also create autocalibration routines that can compensate critical circuits for process, voltage, temperature, impedance, and noise variations while the chip is in use. The only apparent option is to move test-and-measurement instruments—the racks of logic analyzers, bus analyzers, communications testers, and oscilloscopes that populate the bring-up lab—onto the chip itself.

Vitesse has devised a two-channel approach to implementing on-chip receiver instrumentation that supports the generation of an eye diagram or bathtub curve.

To learn how firms including Analog Devices, ARM, Dafca, Rambus, STMicroelectronics, and Vitesse are adding instruments to their devices, see the full-length version of this article, from sibling publication EDN: www.edn.com/article/CA6531583.html.