MIMO challenges existing ATE

You can often adapt existing test systems for new devices, but with MIMO, this approach may not suffice.

By Keith Schaub, Advantest America -- Test & Measurement World, 4/1/2008

2008 promises to be an exciting year for the wireless industry, in particular because many multiple-input multiple-output (MIMO) devices will ramp into high-volume production, enabling increases in data throughput and link range through higher spectral efficiency. In order for MIMO technology to become widely accepted by consumers, it will have to cost about the same as present-day wireless technology. This dictates that test-system manufacturers rein in test costs by developing automatic test equipment (ATE) that can handle MIMO devices during high-volume production.

Today, non-MIMO devices such as multibanded cellphones, with anywhere from two to 10 radios, already ship in volume on ATE. You might ask then, what’s so different and challenging about MIMO, when the ATE industry has been testing multiple-radio systems successfully for several years? The answer lies in the fact that MIMO systems use the radios simultaneously to take advantage of the multipath effect, meaning at any given time they all are “on,” either transmitting or receiving, whereas a multibanded phone has only one radio “on” at any given time. Therefore, to adequately test MIMO devices, ATE systems need an architecture similar to the MIMO systems themselves. Currently, the industry expects to see up to 4x4 MIMO, which will require the ATE to have four independent transmitters and four independent receivers.

This requirement, which will have both business and technical repercussions, is driven by the fact that several key interference signal measurements are performed on radios on ATE systems. Typically, a desired signal plus one or more interfering signals are simultaneously injected into the device under test (DUT) to determine the receiver’s ability to detect the desired signal in the presence of interference, blockers, or jamming signals. This multi-DUT testing has traditionally been accomplished by the use of a splitter that routes the same input signal to several DUTs at once (Figure 1).

Because MIMO takes advantage of the multipath effect, however, this method is insufficient. To assess a DUT receiver’s ability to perform as a MIMO system, the ATE will need to inject it with multiple independent signals with different noise, interfering, and channel characteristics. This means simply using a splitter is not enough.

Instead, manufacturers will need to use quad-site parallel testing for RF/wireless chipsets. ATE systems for MIMO devices will need independent vector signal generators (VSGs) and vector signal analyzers (VSAs) as well as multiple and independent digitizers and arbitrary waveform generators (AWGs), as illustrated in Figure 2.

Another challenge facing MIMO test is the amount of data that the test system must handle. MIMO by definition involves considerable digital signal processing. Combining the processing requirements with the need to test multiple MIMO chips in parallel (that is, quad-DUT 4x4 MIMO) leads to a dramatic increase in the amount of test data captured, transferred across the backplane/bus, and processed. Consequently, meeting the required cost of test (COT) targets can become very difficult.

Some vendors have tried to meet this challenge by providing local digital signal processors (DSPs) or field-programmable gate arrays (FPGAs) to reduce the amount of data transferring and reduce the load on the system computer. While this approach does help to reduce the load on the system backplane (bus) and the system controller, the system controller then becomes the master gatekeeper. As a result, the master controller, which still must make all of the decisions regarding all of the MIMO sites, ends up becoming the bottleneck. Not only does this negatively impact throughput, but site independence is lost.

Fortunately, ATE systems that employ multicore processors can now support independent site controllers; this allows each MIMO site to operate completely independently from the other sites. Effectively, the ATE system behaves as if it were four ATE systems in one, enabling device manufacturers to employ innovative testing strategies that drastically reduce the cost of test. Here are two examples:

• Independent programs can be loaded into each site’s processor, opening up new characterization and production strategies.
• Handler and tester interfacing can be optimized for minimum test time and maximum throughput. Each site “decides” independently what, when, and how to log and bin its DUT.

With total independence architected into the ATE, new testing models can be created, which ultimately allow the target test costs to be realized for both characterization and production testing.

There is still another major burden that parallel MIMO testing imposes on ATE, and that is real estate. Newer ATE systems offer smaller footprints that reduce the initial capital cost for device manufacturers. So, the real estate burden is exacerbated by the fact that not only has the RF pin density increased by a factor of 10, but the layout space on the load board has been reduced because of the smaller-footprint test heads.

A quad-site MIMO solution can potentially require up to 32 RF pins for transmit and receive. Even if the ATE system has enough pins, the traditional RF pins found on most ATE systems are SMA connectors, and SMA pins require too much real estate on the performance board.

To achieve quad-DUT and higher parallelism, the SMA pins will have to be replaced by smaller footprint pins like SMPs. Yet smaller pins will not solve the real estate problem by themselves. The RF signal routing to and from these pins and to and from the test head connectors becomes impractical without additional innovation, such as the use of vertical RF pins and the use of an intermediate layout layer architected into the ATE.

The use of vertical RF pins will eliminate the cutouts that are common on today’s RF boards. Each cutout is a hole that eliminates any possibility of routing signals through it. For a quad-DUT and higher board, the real estate is too valuable to discard, because it is needed for signal routing. The vertical RF pin can minimize or eliminate the cutouts.

Another issue facing system designers is the routing of the test pins. Testers used for system-on-chip (SOC) devices are card based, meaning the customer places the appropriate cards in the test head, and all of the pins for that card interface to a specific Pogo-block or sub-quadrant location (Figure 3). The board designer can now lay out the board, but all of the DUT pins specific to a particular module must be routed to the same Pogo-block location. For devices with only a few RF pins, this is a relatively minor issue.

But the single Pogo-block model quickly breaks down for devices with 32 or more RF pins. For most of the pins, including DC and low-speed digital and low-frequency analog pins, the designer can use the multiple layers of the load board. For RF and high-speed digital pins, however, the impedance is paramount and must remain uniformly at 50 V throughout the board. For that reason alone, RF signal routing is always constrained to be on the top layer. Therefore, routing 32 RF pins on the top layer to a single block interface is not practical without an intermediate layout layer. The intermediate layer distributes resources symmetrically across the load board so designers are able to route the signals symmetrically and uniformly based upon the DUT pinout (Figure 4).

It’s clear that MIMO devices present multiple challenges to the ATE environment. To meet these challenges, most leading ATE companies have either introduced or will soon introduce multiple receiver products. The true challenge now is to engineer a viable, cost-effective, production-worthy ATE solution that manages the multi-RF receiver resource routing issues, optimizes DUT-to-DUT correlation, and minimizes leakage and cross-coupling isolation in the load board.