VMETRO introduces XMC buffer-memory module

-- Test & Measurement World, 4/24/2008 9:29:00 AM

Expanding its embedded computing offerings in the XMC form factor, VMETRO rolls out the MM-6171 buffer-memory node with support for Serial RapidIO and PCI Express. The MM-6171 is a rugged COTS board that provides 2 to 4 Gbytes of high-speed buffer memory.

Primarily used in digital signal processing systems for high-speed temporary storage, expanded system memory, interleaving, and data aggregation and warehousing, the MM-6171 is suitable for embedded applications such as radar signal processing, signal intelligence, and image acquisition that require buffering capability with a FPGA memory controller.

Conforming to the VITA 42 mezzanine standard, the card interfaces to the host through the P15 connector. Four to eight high-speed serial links running at up to 3.125 GHz provide a high-speed full-duplex interface. Connecting these high-speed signals to the memory arrays is a Xilinx Virtex-5 LX50T FPGA. The device serves as a memory controller and is not designed to host User Programmable Logic (UPL) inside of it. Off of the LX50T are two independent memory arrays, each capable of interfacing to 1 to 2 Gbytes of DDR2 memory. Each array is 72-bits wide, with a 64-bit data path and ECC. Single-bit errors are corrected and double-bit errors are detected through the memory controller’s logic. The DDR2 arrays provide over 3 Gbytes/s of data bandwidth.

The MM-6171 also includes a Serial RapidIO or PCI Express interface and DMA engine. The Serial RapidIO x4 interface runs at 3.125 GHz with a corner-turning, striding DMA engine for advanced functionality in DSP systems. For PCI Express applications, the x8 bus interface runs at 2.5 GHz and also provides a full-featured DMA engine.

VMETRO provides MM-6171drivers for VxWorks 6.x and Linux 2.6.x. The MM-6171 comes in commercial, convection-cooled, and ruggedized, conduction-cooled variants.

VMETRO, www.vmetro.com.