Test methodologies for high-speed serial designs
Rick Nelson, Editor in Chief -- Test & Measurement World, 5/1/2008
The first generation of serial standard applications is already well established, and the move to the second and third generation is underway, says Randy White, high-speed serial-applications technical marketing manager at Tektronix, in the Webcast “Overview of the Latest Test Methodologies for High Speed Serial Designs.” Time to market is critical, he adds, noting that delays of product introductions usually have big financial consequences.
 When designing high-speed serial communications links, engineers must understand all the interactions between transmitter, channel, and receiver. |
Making delays more likely, White says, is the fact that engineers face greater technical challenges to be solved, as they deal with design elements such as pre-emphasis effects at the transmitter output and the equalization employed to compensate for signal loss at speeds above 2.5 Gbps. In short, they must understand all the interactions between transmitter, channel, and receiver (figure), and they must also understand the effects that their measurement systems will have on performance.
During the Webcast, White provides details on digital validation and debug, serial data link analysis (SDLA), receiver testing, and signal integrity and compliance testing. In particular, he notes that SATA, PCI Express, and Gigabit Ethernet, for example, now require S-parameter measurements in their compliance test procedures, and he describes S-parameter measurement tools based on a time-domain reflectometer (TDR) that are accurate and easy to calibrate and that deliver high throughput.
In addition, White describes how to apply limit, stress, and compliance tests for receiver designs. You can view the archived version of this Webcast, presented live on March 17 and sponsored by Tektronix, Test & Measurement World, and EDN, at www.tmworld.com/webcasts. A video demonstration of an automated compliance test is also available.
