From tape-out to yield

Presto Engineering founder and CEO Michel Villemain said that manufacturers have shied away from backside analysis because of its complexity, but he adds that the technique is becoming indispensable at the 65-nm process node.  Photo by Gary Laugman.

The company’s goal is to complement customers’ in-house product-engineering, test, and failure-analysis capabilities when chip makers find their expertise in one or more of these areas is scarce, or where unusual test requirements would otherwise dictate the purchase of equipment that would be too costly to bring in house. Deficiencies that Presto can address might include lack of the equipment and trained personnel necessary to handle backside in-circuit analysis (photon emission measurement, laser stimulation/analysis, laser voltage probing, and backside focused ion-beam [FIB] probing) in combination with automated-test-equipment (ATE) operation and programming.

Presto Engineering occupies the 10,000-ft² test floor formerly owned by Cypress Semiconductor, dedicating three-shift operation to provide test, fault-isolation, and failure-analysis services, according to Michel Villemain, founder and CEO. The goal, he said, is to complement, not displace, traditional test houses and analytical labs (Figure 1).

Figure 1.  Able to provide test and analysis services, Presto Engineering works with product engineering, test houses, and analytical labs.

Villemain is well positioned to tailor the available equipment to test and analysis applications, having served most recently as marketing VP for the circuit-edit and mask-repair division at FEI. He was also GM of the CD-SEM business unit at KLA-Tencor, and he began his career in the semiconductor test industry with Schlumberger (which later became NPTest, which in turn was bought by Credence Systems), where he worked in the company’s ATE and probe-systems divisions.

Figure 2.  Capabilities that Presto Engineering offers include PrestoConnect, which operates from tape-out to first silicon, and PrestoPE, which operates during ramp-up to profitable yield.

Villemain said Presto employs a variety of fault-isolation and failure-analysis techniques, including mechanical probing for electrical measurements as well as laser-based techniques (to localize faults to specific vias) and emission-based techniques (for examining transistor performance). The company complements those tools with scan-based localization to pinpoint defective gates. “I’m a big believer in scan test,” he said, “and we are trying to push and expand the coverage of scan test for validation and characterization and analysis as much as we can.”

Cost is one factor that makes scan test attractive, Villemain said, presenting a graph (Figure 3) of per-pin test costs and total tester costs over the last 23 years. Today, a dedicated scan tester costs between $200,000 and $400,000, compared with almost $8 million for a 400-MHz functional tester in 1995. On a per-pin basis, 512-pin scan tester costs can be as low as $500 per pin, compared with more than $15,000 per pin for a 1990 Schlumberger ITS 9000FX with 192 pins. Going forward, Villemain said, “The whole concept of DFT [design for test] and investing up front to reduce cost downstream is going to be very pervasive. The cost equation for test has been completely reset.”

Figure 3.  Presto Engineering deploys a dedicated scan tester, which delivers 512-pin performance at approximately $500 per pin today, demonstrating how tester prices have fallen from a high per-pin cost of $15,000 for a Schlumberger ITS 9000FX in 1990 and a high total cost of $8 million for a high-end 400-MHz machine in 1995.

This approach, as he explained it, uses a scan tester for validating all circuitry accessible via scan or built-in self-test (BIST). I/O characterization can then take place on the customer’s target production tester. As to what that production tester should be, he said, “Presto is tester-agnostic.”

The dual-platform approach, he said, can offer significant savings, especially if Presto’s customer can supply standard test interface language (STIL) or WGL files, enabling Presto engineers to bring up the scan-test program in a day or less. Describing a typical bring-up scenario, Villemain said that five weeks of characterization on a functional tester can cost $60,000. Alternatively, the dual-platform approach requires four weeks on a scan tester for $16,000, in parallel with two weeks on the functional tester, costing $24,000, for a total characterization cost of $40,000, resulting in a $20,000 savings.

When factoring all project functions, ranging from load-board development to the porting of BIST vectors to production ATE, the dual-platform approach, he said, can yield a total project cost of only $167,000 with a 17-week turnaround vs. $242,000 with a 21-week turnaround for a functional-ATE-only approach.

Villemain said he expects the need for his company’s services to expand as process geometries shrink. At the 130-nm node, he said, manufacturers supported 46 captive product-analysis labs in North America, while at the 65-nm node, the number is only 12—but not because chips are sailing into production without any re-spins. In fact, Sauk estimated that fewer than 40% of IC designs go to production with first silicon.

Villemain sees three reasons for the reduction in the number of captive test houses:

• the cost of 65-nm-capable equipment,
• the necessary transition from front-side to backside analysis, which requires hard-to-develop and hard-to-retain expertise, and
• the complex requirement of combining test equipment with analysis equipment to provide stimulus during the analysis process.

Companies that rarely need such equipment and expertise, he said, cannot justify the huge investment necessary to bring the required analytical capabilities for new process nodes in house.

Villemain and Sauk both emphasized that backside analysis is definitely necessary because the increasing number of metal layers is preventing front-side analysis. “The traditional toolset used to isolate faults—such as metal-centric (front-side e-beam) probing and FIB circuit edit—become very difficult to use when you have more than three or four metal layers and buried elements become harder to access,” said Sauk. But, added Villemain, “There is a perception gap, causing manufacturers to avoid backside analysis for fear it’s too complex and won’t work.”

Villemain acknowledged that backside analysis tools are complex and require much practice to use effectively. In addition, the techniques can be conceptually difficult to understand. “E-beam was difficult enough, but it was fairly simple to explain—you have electrons in and secondary electrons out,” he said. “But how do you explain all these laser-related techniques? It’s very arcane.”

Complicating the matter, he said, is the fact that “backside measurements are proxy measurements…your transistor switches and emits a photon once in a while. You need mentally to bridge what you see on your photon-emission system’s screen to what you need to understand about your product. Now, e-beam is a proxy measurement, too, but it’s a simple proxy. The other techniques are more complex and require a lot of interpretation. So, there is a knowledge gap.”

But despite the complexity of backside analysis, he said, “I’ve been providing these tools for 10 years now, and I’ve seen them in operation in a lot of labs. Backside analysis does require different approaches, but it does work. It’s a perception gap that is really an issue that needs to be bridged.”

Villemain cited other issues that complicate test and analysis, including the transition from predominantly random defects to predominantly systematic ones. Addressing systematic defects requires close links between design, test, and analysis. In addition, he said, many defects in advanced processes are soft—occurring only at certain voltages or temperatures, for example. If a soft error occurs only at –40°C, he said, you need to be able to duplicate that condition during backside analysis.

Sauk elaborated on the difficulty that can occur during backside analysis. You need to remove any existing fans, lids, or heat sinks to provide visibility into the silicon, yet you need to retain a way to control the temperature. For that, Presto uses heat spreaders that provide temperature control while enabling visibility into the device under test.

Frank Sauk, Presto Engineering’s co-founder and engineering VP, works with Presto’s Allegheny prototype for temperature and high-power SIL characterization. Photo by Gary Laugman.

He added that soft errors caused by cosmic rays and alpha particles continue to be a primary concern as well for memory and logic designs targeting 65 nm and smaller processes. Presto, Sauk said, has recently established a collaborative sales and service relationship with iRoC Technologies, allowing customers in North America access to the SERTEST soft error rate testing services.

To help take chips from tape-out to high-volume production, Presto deploys an Ocelot ATE system for scan test. It has on hand a SEMICAPS SOM 4000 scanning-optical microscope, which combines a photo-emission microscope and laser-scanning microscope for fault isolation. A Schlumberger IDS 10000 plus e-beam system and mechanical probers support electrical failure analysis.

In addition, Presto partners with Nanolab Technologies, which is located near Presto’s facility, to make available a Sonoscan C-SAM scanning-acoustic microscope, an FEI NanoSEM 630 scanning-electron microscope (SEM), an FEI V-600 FIB system, a JEOL 3010 transmission-electron microscope, and an 8-in.-wafer-capable FEI 855 dual-beam FIB/SEM system. Other capabilities include sample de-cap and de-processing, backside sample preparation, deep ultraviolet microscopy, and real-time x-ray.

The company’s PrestoConnect service extends from tape-out to first silicon, while PrestoPE (the PE stands for “product engineering”) extends from first silicon to high-volume production. Services include packaging, docking assemblies, thermal interfaces, load-board development, cooling design, validation, characterization, test engineering, electrostatic discharge/latch-up troubleshooting, environmental screening, debug, fault isolation, failure analysis, and root-cause analysis.

The initial point of engagement with customers is packaging, Sauk said. Presto provides analysis-ready packages—including backside-ready packages for wire-bonded devices—that work with standard load boards. “When we sit down with customers, we go through a process in which we determine pad count, pad pitch, die size, and wire length.”

Presto now offers 680- and 532-ball ball-grid arrays (BGAs) and 256-pin pin-grid arrays (PGAs); the company will design and build new packages when necessary. The packaging process—including die-attach and wire-bonding, encapsulation and ball-attach, and sample preparation (including thinning and polishing)—takes about a week, Sauk said, with yields of 90%. For analysis of field returns, the repackaging process (including parallel polishing down to wire-bond balls, die-extraction, die-attach, wire-bonding, encapsulation, ball-attach, and sample prep) requires a turnaround time of about two weeks and offers a yield of 60% to 80%.

With access to the backside, Sauk said, “we can do time-resolved emission and laser scanning, and even e-beam is making a resurgence.” E-beam techniques, he said, derive some timing and voltage information not available with other approaches. “Each of these techniques has strengths,” Sauk said, “but each has gaps as well.”

The ability to understand where the gaps lie and compensate for them will be key to getting next-generation chips to market. As process geometries continue to shrink and the number of metallization layers increases, effective failure analysis will become increasingly important. But on a final note, Villemain suggested—facetiously—that failure analysis might disappear as a discipline. “My marketing team tells me 'failure analysis’ has a bad connotation. What we provide at Presto is 'design success analysis.’”