From system-level design to hardware prototypes

STMicroelectronics at the Mentor Graphics booth highlighted an electronic-system-level (ESL) reference design flow that is integrated with Atrenta’s SpyGlass for register-transfer-level (RTL) lint-checking and power-analysis tool as well as Mentor’s Catapult C synthesis tool and Calypto Design Systems’ sequential logic equivalence checker (SLEC). Atrenta at its booth announced its 1Team-Genesis product, which spans design-specification capture through correct-by-construction chip assembly. ST representatives were on hand at the Atrenta booth to explain that 1Team-Genesis forms the basis of a collaborative effort in the area of power estimation and management.

Virage Logic demonstrated an open RTL-to-test-floor embedded-memory test-and-repair subsystem based on the company’s Self-Test and Repair (STAR) memory system and yield accelerator. Virage also announced support for TSMC’s Power Trim Service technology, which helps control leakage. Apache Design Solutions announced that TSMC’s Reference Flow 9.0 accommodates Apache’s technology for jitter, power, noise, and leakage analysis.

Berkeley Design Automation announced a co-simulation capability for its Analog FastSpice circuit simulator with third-party Verilog hardware-description-language (HDL) simulators. Extreme DA and UMC announced their collaboration on variation-aware IC design flows for 65-nm and finer process technologies. The flows predict design performance and yield by analyzing timing behavior in the presence of process variations.

National Instruments was one of the few companies to have hardware on display to complement software offerings. NI highlighted an automated chip characterization and validation system based on LabView and PXI instruments. NI also demonstrated a prototype field-programmable-gate-array (FPGA)-based engine-control system put together by Drivven.