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STC to help test keep pace with design

Rick Nelson, Editor in Chief -- Test & Measurement World, 7/1/2008

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Design productivity is outpacing test capabilities—that's one conclusion to be drawn from the global Semiconductor Test Consortium (STC) conference held June 4–6 in San Diego. That situation has implications for areas ranging from instrumentation to education, according to conference presenters.

Don Edenfeld of Intel laid out the implications for instrumentation in his presentation as chair of the STC's as-yet unofficial Portable Test Instrument Module (PTIM) working group. To emphasize the need for a PTIM standard, Edenfeld cited a scenario in which last-minute design changes mandate test capabilities not available in existing native ATE system instruments—such as those complying with the STC's OpenStar standard. Development of a new ATE-class instrument that could provide the necessary capabilities might represent a $2 million investment over 18 to 24 months, he said, making the time and cost prohibitive.



Two PTIM options would offer either the integration or the performance levels of native semiconductor ATE instrumentation. A third option would leverage existing instrument platforms like PXI.

Edenfeld said that because of gaps in existing standard instrument platforms like PXI and GPIB, working group participants ruled them out, but based on a subsequent evaluation of the time and expense necessary to develop a new platform, existing platforms are back under consideration.

Luke Schreier of National Instruments made the case for PXI as the basis for a PTIM standard. He presented a picture (figure) in which two PTIM options offer the system-integration capabilities or the performance of native-mode ATE instruments, but at high development costs and with long turnaround times. He proposed a third option that would complement the integration and performance of native ATE instruments while leveraging an existing instrument platform.

PXI would serve well as that platform, Schreier said, because of the breadth of instruments already available, including digital, RF, and precision DC instruments; arbitrary waveform generators; digitizers; and clock generators.

Edenfeld said a draft standard could be available in the third quarter with a final spec completed by year's end.

Paul Roddy of Advantest laid out the implications for education in a presentation titled “Aligning Academia with Leading Edge Semiconductor Test Technology.” Roddy, a co-chair of the STC University Working Group (UWG), said the group is working to align academic programs with industry needs, establish a global database for test research projects (to avoid duplication of effort), partner with other organizations to promote research, and set up a repository for test-engineering curricula.

Specific efforts of the UWG, Roddy said, include putting OpenStar testers in university labs and working with organizations such as Science-Engineering-Technology Congressional Visit Day (www.setcvd.org) and Alliance for Science & Technology Research in America (www.aboutastra.org). Such efforts, he said, can reduce the six to 18 months it now takes new engineering graduates to become fully integrated into industry test projects—with a concomitant reduction in the time senior engineers need to train them.

 

Handler technique passes customer test
Multitest has announced that its “voice coil” pick-and-place handler technology passed an evaluation at a German production site of an international integrated device manufacturer (IDM). The voice-coil principle—used to control the z-axis height while placing a device under test—increases overall test cell efficiency by speeding device handling, the company reports; Multitest also says that the technique is particularly suitable for applications with short test times and high parallelism. www.multitest.com.


UTAC Taiwan acquires V93000 HSM2200 systems

Verigy has announced that United Test and Assembly Center Taiwan (UTAC Taiwan), a semiconductor test and assembly service provider, has acquired multiple V93000 HSM2200 high-speed memory test systems for high-volume production of DDR3 devices. DDR3 features per-pin data rates of up to 1600 or 2133 Mbps, doubling the maximum data transfer rates of DDR2. www.utacgroup.com; www.verigy.com.


Teradyne's Nextest unit ships 2000th tester

Teradyne has announced the shipment of the 2000th test system from its Nextest business unit. “This significant milestone underscores the success of Magnum and its ability to provide customers with compelling test solutions from engineering through the critically important high-volume production process,” said Tim Moriarty, GM of the Nextest business unit. www.teradyne.com.

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