Verigy debuts Inovys Silicon Debug technology for V93000
-- Test & Measurement World, 7/1/2008 10:32:00 AM
Verigy has introduced the Inovys Silicon Debug technology to address the need for more efficient debug to accelerate time to volume production of new system-on-chip (SoC) devices. Verigy's new approach combines Inovys FaultInsyte software with the Verigy V93000 SOC test system.
The combination reduces the time required for fault detection and diagnosis by mapping electrical failures to physical defects on complex SOC devices with the goal of shortens time to debug and ramp to volume production for manufacturers using deep submicron processes for which design is more of a problem than dirt—that is, particulate driven yield loss is dwarfed by design-driven yield loss. The V93000 and FaultInsyte combination provides for real-time analysis to eliminate the weeks required to observe a fault, retest, capture data, simulate faults, perform layout extraction, and search for a physical defect.
The new approach is advantageous, Verigy says, because designs at and below the 90-nm process node are highly sensitive to fabrication equipment variation, leading to new defect mechanisms and fault models. In addition, at this scale, process and design interactions introduce new, complex failures and defects.
"Accelerating the detection and diagnosis of design-induced failures is essential to achieving time-to-market for complex SOC devices. At the latest process nodes, the advantage of a few weeks to market can mean millions of dollars to the designer," said Hans-Juergen Wagner, VP and GM of Verigy's Semiconductor Test Solutions. "The Inovys Silicon Debug Solution, integrated with the measurement capabilities of the V93000, provides a unique tool. Manufacturers can now find previously elusive faults while the complex SOC devices are still on the tester and without invoking expensive and time-consuming systems and processes."
The hardware/software combination takes advantage of the V93000’s large fail-capture memory, measurement repeatability, and per-pin architecture, Verigy reports, adding that the Inovys FaultInsyte technology provides visualization and diagnostic tools that offer views into the "structural DNA" of the semiconductor device. The Silicon Debug capability can be added to existing V93000 Pin Scale systems. Verigy is currently working with early-adoption customers, and the solution will be widely available beginning November 2008.
In related news, Verigy announced that STATS ChipPAC has purchased the Verigy Port Scale RF platforms for multi-site testing of highly integrated wireless devices containing RF, mixed-signal, digital, power management, and embedded or stacked memory. "Verigy’s Port Scale RF solution will help position STATS ChipPAC with capability to meet current and future demand for quick ramp-up and volume manufacturing of our customers' advanced RF devices," said Wan Choong Hoe, executive VP and COO of STATS ChipPAC.
Verigy also said that NVIDIA has significantly expanded its existing fleet of V93000 SOC testers. NVIDIA uses the V93000 for high-speed design characterization and also in volume production for its semiconductor devices for workstations, personal computers, game consoles, and mobile devices. NVIDIA populated its V93000 systems with Verigy's Pin Scale 400 channel cards. "Verigy continues to provide a solution that meets our performance and flexibility needs along with outstanding service and support," said Debora Shoquist, senior VP of operations at NVIDIA. "Verigy has been a strategic partner for us and we are happy to expand the relationship.”
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