Selecting op amps for high-speed ATE digitizers
Maurizio Gavardoni, Maxim Integrated Products -- Test & Measurement World, 7/29/2008 10:03:00 AM
Digitizers play a fundamental role in testing state-of-the-art devices for applications such as DVD, DSL, cellular phones, HDTV, and set-top boxes. The digitizer is an option for ATE systems that capture analog signals in bandwidths from DC to several hundred megahertz, and convert them to digital format for signal processing with digital signal processors (DSPs).
High-performance digitizers employ analog-to-digital converters (ADCs) of 12- to 16-bit resolution, with sampling frequencies of 100 Msps or so. The high resolution allows accurate testing of linearity for most of the digital-to-analog converters (DACs) used in HDTV, set-top boxes, and similar-performance products. One requirement for digitizers is a high bandwidth that approaches the ADC sample rate and even beyond, if the ADC is to implement under-sampling techniques.
At the other extreme, it is also important to extend the analog bandwidth down to a very low frequency or DC. To increase the cost benefit of investing in a high-bandwidth digitizer, the test engineer will want to use it for testing lower-bandwidth devices as well.
As a fundamental feature of automated test equipment (ATE) digitizers, the selectable input-voltage range lets you handle applications in which the typical input signals vary from 4 VP-P down to 250 VP-P and lower. An ADC with the performance mentioned (16-bit resolution and 100 Msps) might have an input full-scale range of 2 VP-P to 2.5 VP-P, with a common-mode input range of 1.5 V to 3.5 V. The digitizer’s analog chain must therefore provide a programmable “scaling factor” that accommodates the wide input ranges and feeds them to the ADC.
Figure 1. A typical ATE digitizer executes analog tests on a DUT (device under test) and delivers digital results on an ATE bus.
Figure 1 shows the block diagram of a typical ATE digitizer and the device under test (DUT). Light gray indicates the analog input chain, which consists of an amplifier with selectable input range (the subject of this article), low-pass antialiasing filter, and fully differential ADC driver. The PMUPP block implements the parametric-measurement-unit per-pin function used for open/short and other DC tests. The darker gray indicates digital circuitry: the ADC, the DSP, and the bus that connects the instrument to the test system.
Assuming a 2 VP-P differential input-voltage range for the ADC, the question is: What circuit topology and what amplifier types best fit the first block of the input analog chain, which must accommodate a wide input voltage range (4 VP-P to 250 mVP-P differential) and condition it for the ADC input? (To achieve an optimum signal-to-noise ratio, all analog inputs to the ADC should fall in the upper half of its range.) Also, of course, each input-range selection must guarantee the same analog bandwidth.
Choose optimum amplifiers and circuit topology
The circuit topology discussed in this section offers key advantages. First, it includes current-feedback op amps whose gain can be varied without affecting bandwidth (see "Current-feedback amplifiers implement digitizers"). Input ranges are switched by switching the gain of the op amps, which is accomplished in turn by changing the value of Rg associated with each op amp. Second, the digitizer’s closed-loop bandwidth, phase margin, and stability remain unaffected because the value of feedback resistance (Rf) doesn’t change. These points are further explained in the following discussion.
The input amplifier must have high input impedance, programmable gain, differential inputs, constant high bandwidth for each selected gain, low noise, and low distortion compatible with the linearity performance of 14- and 16-bit ADCs (Table 1). CMRR and PSRR are also important characteristics.
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Table 1. Typical specs for high-performance 14/16-bit ADCs |
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Parameter |
Condition |
Typical value |
|
ADC sample frequency |
|
More than 100 Msps |
|
ADC resolution |
|
14 to 16 bits |
|
Large-signal input bandwidth |
Any input range |
200 MHz |
|
Input voltage ranges |
Differential inputs |
4 V, 2 V, 1 V, 0.5 V, 0.25 V |
|
Input impedance |
Any input range |
>100 kΩ |
|
Common-mode rejection ratio |
Any input range at 1 kHz |
60 dB |
|
Common-mode rejection ratio |
Any input range at 1 MHz |
40 dB |
|
SNR |
@ 1 MHz |
>70 dB |
|
SNR |
@ 20 MHz |
>55 dB |
|
THD |
@ 1 MHz |
<–80 dB |
|
THD |
@ 20 MHz |
<–55 dB |
An integrated amplifier compatible with these characteristics does not exist, but the building blocks for such an amplifier include op amps, precision resistors, and relays (or analog switches) for making gain selections. The main challenges are the choice of op amp and the choice of circuit topology necessary to implement programmable gain changes while maintaining a constant high bandwidth of several hundred megahertz. Table 2 lists the op-amp gain associated with each input voltage range (VP-P).
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Table 2. Gain vs. VP-P |
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VP-P |
Gain |
|
4 |
0.25 |
|
2 |
0.5 |
|
1 |
1 |
|
0.5 |
2 |
|
0.25 |
4 |
Referring again to Figure 1, the requirements assume that the ADC has a 2-VP-P full-scale differential input and is driven by a single-ended-to-differential amplifier (ADC driver). The combined ADC driver and antialias filter has a gain of 2. The input amplifier, therefore, must provide a single-ended output with 1-VP-P swing.
 Figure 2. This gain-switching network from an ATE digitizer eases the burden on any one op amp by allocating gain to U3 as well as the U2-U2 combination. |
To avoid having to configure a single op amp for gains ranging from 0.25 to 4, the circuit topology should allocate gain across multiple stages. This approach (Figure 2) minimizes even the small variations in closed-loop bandwidth caused by varying the Rg resistor. Table 3 shows the switch states corresponding to each selected gain range in Figure 2, where G1 represents the gain of the first stage (consisting of U1 and U2) and G2 represents the gain of the second stage (U3).
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Table 3. Switch states vs. gain range |
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|
T1 |
T2 |
T3 |
G1 |
G2 |
Overall gain |
|
open |
open |
open |
1 |
0.25 |
0.25 |
|
closed |
open |
open |
1 |
0.5 |
0.5 |
|
closed |
closed |
open |
1 |
1 |
1 |
|
closed |
open |
closed |
4 |
0.5 |
2 |
|
closed |
closed |
closed |
4 |
1 |
4 |
Input amplifiers U1 and U2 can have either unity gain or gain of 4. A low-noise, low-distortion current-feedback amplifier is the best choice for this stage, as explained later. The low-noise requirement is very important, because this amplifier is the first stage of the analog chain. Gain in the initial chain can be as low as one, however, so the low-noise requirement is also important for differential amplifier U3. CMRR (common-mode rejection ratio) depends on U3 (the second stage), and especially on the accuracy of the resistor values. This circuit topology offers high input impedance regardless of the selected input-voltage range.
The high-bandwidth requirement (several hundred megahertz) suggests the use of current-feedback amplifiers. The wideband capability of these devices may not be their main attraction, however, because today’s voltage-feedback amplifiers can deliver comparable bandwidth performance. The main reason is the ability of a current-feedback op amp to cope with different gains while delivering the same bandwidth for each. This behavior is particularly important for the input-stage amplifiers U1 and U2, which must switch between gains of 1 and 4. Constant bandwidth is not easily achieved with voltage-feedback amplifiers, because their gain-bandwidth product is constant.
A current-feedback amplifier in a small SOT23 package (MAX4223) matches all the requirements of Table 1 and is suitable for amplifiers U1, U2, and U3 of Figure 2. It features a large-signal bandwidth greater than 250 MHz and stability at any level of gain. When not too heavily loaded, it also provides very low noise and low distortion.
As mentioned, the closed-loop bandwidth for a current-feedback amplifier depends on the value of feedback resistor Rf. Lower Rf values allow higher bandwidth but lower phase margin, so amplifier stability also depends on that resistor. Because the current-feedback topology allows a change of gain without changing the feedback resistor, gain changes don’t alter the amplifier stability.
At least, the above statement is true if you assume that second-order effects are negligible (such as stray capacitance at the inverting node). In fact, stray capacitance at that node introduces a pole in the open-loop gain, and therefore plays a fundamental role in the amplifier’s stability. Stray capacitance is an important consideration during board layout. The goal is to minimize, at the inverting nodes, any stray capacitance that might be introduced by the relays. For that reason, T2 is placed across the R resistors immediately driven by the output of the first stage, and not across the R resistors that drive U3. For similar reasons, T3 is “buffered” by the two resistors R/3.
The current-feedback amplifier must have low noise and low distortion, but amplifiers of that type also have drawbacks that present a major problem in many applications. One such drawback is the high static current draw and consequent power dissipation; another is the limited DC accuracy due to input offset. A third source of problems caused by this circuit topology is the dependence of common-mode rejection and gain accuracy on the precision of external resistors.
ATE manufacturers, though, are willing to pay the premium necessary to get high-frequency performance. High static current, power dissipation, and the resulting temperature drifts can be handled by sophisticated liquid-cooling systems that maintain electronic boards and components at a constant and controlled temperature. Offset, gain error, and common-mode asymmetry can be eliminated with system software calibrations.
ATE instruments include low-speed DACs that drive calibration circuits, which in turn remove offset from the analog chain, compensate for gain error, and adjust resistor values, thereby compensating for circuit asymmetries that would otherwise degrade the common-mode rejection. Such DACs are typically controlled by FPGAs or ASICs, and controlled by software calibration algorithms that run before the ATE tests are executed.
This article has described challenges faced by ATE vendors in the design of high-speed, high performance digitizers for testing state-of-the-art devices in applications such as DVD systems, set-top boxes, and HDTV. Digitizers offer multiple input-voltage ranges, and one challenge is to provide similar values of analog bandwidth, noise level, and linearity for each input range. We propose a circuit based on op amps to solve this problem, and demonstrate why a current-feedback topology may be the preferred choice for such op amps.
Maurizio Gavardoni is a product definer for amplifiers and comparators in the multimedia business unit of Maxim Integrated Products, Sunnyvale, CA. Prior to joining Maxim, he worked for ten years as a mixed-signal designer in several ATE companies. He holds bachelor’s and master’s degrees in electrical engineering from the University of Milan, Italy.
Mixed-signal instruments called digitizers are used in the ATE (automated test equipment) industry to capture analog signals and convert them to digital format for further signal processing. The trend for such instruments in the high-frequency arena is toward 16-bit resolution, with sampling frequencies of 100 Msps and higher.
One challenge in designing such instruments is to maintain a relatively constant analog bandwidth for the various input-voltage ranges that can be selected. Typical input ranges vary from 4 V down to 250 mV, in 6-dB increments (4 V, 2 V, 1 V, 0.5 V, 0.250 V). The analog acquisition chain should guarantee the same input analog bandwidth (a few hundred megahertz) regardless of the input range selected. These analog chains are usually designed with current-feedback op amps, precision resistors, and either relays or analog switches for selecting the input range.
Changing the input voltage range subjects an op amp to different values of gain or attenuation. The designer must therefore select an op amp that provides constant analog bandwidth as it operates in different gain configurations. This article explains why current-feedback amplifiers are most suitable for these applications, and suggests a specific circuit topology that allows constant analog bandwidth across multiple ranges.
Background on current-feedback amplifiers
Figure A. These simplified block diagrams depict a current-feedback amplifier (left) and its inverting gain configuration (right).
Figure A shows the internal blocks of a current-feedback amplifier and its non-inverting configuration with closed-loop gain equation. A current-feedback amplifier has a unity-gain buffer between its inputs, which forces the inverting-node voltage to follow the noninverting-input voltage. The buffer presents a low impedance at the inverting port, where the amplifier can sense a low-level error current and pass it to the output through a transimpedance gain. This internal transimpedance Z(s) provides the dominant pole and high DC gain characteristic of all op amps. The equation of open-loop gain for the inverting amplifier is
Gloop(s) = -Z(s)*(Z-//Rg)/(Rf+(Z-//Rg)*1/Z-,
where Z- is the impedance of the inverting input. Ideally it is zero; in reality it should be very low. Notice that if Z- << Rg, the equation becomes
Gloop(s) = -Z(s)/(Rf+Z-) ~= -Z(s)/Rf.
Open-loop gain depends only on one external component, the feedback resistor Rf. Resistor Rg does not appear in the equation. Because closed-loop bandwidth is determined by the poles of the open-loop gain, it does not depend on the value of Rg. Assuming that Z(s) has one dominant pole and the op amp is compensated for unity gain (thus all other poles are above the frequency at which amplifier gain crosses the x-axis), the equation of open-loop gain becomes
Gloop(s) = - Z(0)/Rf * 1/(1+sτ)
This equation is represented in Figure B, where τ is the time constant of the op amp’s dominant pole. The area between the curves 20LogZ(f) and 20LogRf represents the open-loop gain. The closed-loop bandwidth is given by the frequency at which these two curves intersect.
 Figure B. This Bode plot (open-loop gain plot) illustrates the response of a current-feedback amplifier with a dominant pole and unity-gain compensation. |
Note that reducing the value of the feedback resistor (Rf) increases the closed-loop bandwidth. A smaller Rf also increases peaking in the frequency response, because it reduces the phase margin and promotes interaction with the op amp’s higher-frequency poles. The closed-loop gain equation is
G(s) = (1+Rf/Rg)/(1-Gloop(s)) = (1+Rf/Rg)/(1+Rf/Z(s)).
You might conclude that current-feedback amplifiers do not have the constant gain-bandwidth product found in voltage-feedback amplifiers. If, however, the value of Rg is sufficiently higher than the low impedance of the inverting node, you can vary the amplifier gain by varying Rg without affecting the amplifier’s bandwidth.
