Accellera updates Verilog-AMS standard
-- Test & Measurement World, 8/21/2008 10:44:00 AM
Accellera, an organization that develops electronic design automation (EDA) standards, reports that its board of directors and technical committee members have approved Verilog-AMS 2.3, a new version of the Verilog-analog mixed-signal (AMS) standard covering design and simulation. Verilog-AMS 2.3 unifies the Verilog-AMS 2.2 specification with the IEEE 1364-2005 standard that defines the Verilog hardware-description language.
According to Accellera, Verilog-AMS 2.3 will enable users to develop tightly integrated Verilog-AMS modules and allow EDA software tool developers to implement EDA tools without ambiguities in the interpretation of the language. Verilog-AMS 2.3 also introduces new analog and mixed-signal features that support improved top-down AMS design and verification methodologies. These include enhancements to table_model, support for multiple analog blocks, and resolution of language conflicts with the SystemVerilog IEEE Std. P1800, such as, changing the digital domain name to ‘ddiscrete’ from ‘logic’ (because ‘logic’ is a keyword in SystemVerilog), and making the use of array literals consistent.
www.accellera.org/activities/verilog-ams
