iNEMI addresses board quality

The International Electronics Manufacturing Initiative (iNEMI) consortium of companies has initiated three projects intended to help manufacturers improve the quality of printed-circuit boards (PCBs). One project aims to establish a standard methodology for assessing functional-test fault coverage, the second will encourage wider adoption of boundary scan by components manufacturers, and the third aims to establish a method for testing the mechanical performance of printed-circuit assemblies.

iNEMI’s stated mission is to identify and close technology gaps by encouraging the accelerated deployment of new technology, the development of industry infrastructure, the dissemination of efficient business practices, and the stimulation of standards. The consortium executes projects through Technology Integration Groups (TIGs) organized around specific areas identified in an iNEMI roadmap that assesses the industry’s most critical needs. Figure 1 presents the roadmap’s basic project model. Board-level projects are being pursued through the Board and Systems Manufacturing Test TIG chaired by Rosa Reinosa from Hewlett-Packard and J.J. Grealish of Intel.

Figure 1.  The basic flow chart for projects initiated through iNEMI TIGs shows that the organization consults with manufacturers as well as with academics and government bodies. Source: iNEMI 2007 Test, Inspection, and Measurement Roadmap. Courtesy of iNEMI.

The first project begun under iNEMI’s board-test TIG seeks to create a quantitative model to estimate and predict functional-test fault coverage. Tony Taylor, test-development engineer at Intel, originally proposed the idea to a forum of board manufacturers and equipment suppliers in Taiwan in 2006. Forum participants wanted feedback from the wider industry in order to establish consistent guidelines, and they suggested that Taylor work with iNEMI. Chaired by Taylor, the project involves a number of otherwise highly competitive companies that have maintained an atmosphere of cooperation, recognizing that the result of their work will benefit everyone.

“We understood from the beginning that functional test was fundamentally different from structural techniques like in-circuit test [ICT] and automated-optical inspection [AOI],” commented Taylor. “Those approaches permit a fairly consistent fault-coverage methodology because they rely on relatively predictable criteria and utilize vendor-supplied equipment.”

He added, “Functional test has to run at speed and in the product’s native environment. Monitoring a board’s performance using conventional rack-and-stack instruments or cards with different features from different vendors inevitably produces a wide variety of results. Also, in a functional test you can narrow a problem down to the circuit elements that perform a particular function, but not necessarily to the condition or behavior of a single component. There is no way to fully automate fault-coverage analysis.”

The group realized early on that although the various board-test techniques overlap to some extent, functional test can provide information about circuit performance that structural test cannot. The goal was to reinterpret functional tests in terms of their structural equivalents where possible, add functional-test’s unique coverage capabilities, and create a framework that companies throughout the industry could use as a reference. iNEMI would then release the results.

“We wanted to involve companies representing all perspectives in board test,” Taylor continued. “Participants brought with them unique points of view and a vast array of experience. The project will begin by laying the methodological groundwork. Then, the companies will implement the approach and provide feedback on its validity.”

One concern in creating a methodology is determining the assessment criteria. An initial paper analysis—in which engineers analyze board schematics and test code—will provide a first-pass specification on how to determine whether a test program covers a board’s critical features. The paper analysis alone will generally suffice for inexpensive or low-margin boards featuring primarily stable technology. Observing the test by hooking a board up to actual instruments can increase confidence in the paper analysis, but it adds to the cost and time required. Test budgets may not permit these extra steps on inexpensive boards, boards with high component counts (which dramatically increase assessment time), and high-complexity circuits that can render fault-coverage determination both time-consuming and ambiguous.

If the product warrants a high-confidence fault-coverage assessment, an additional step will inject faults to determine whether running the test on a board with a known defect will identify the defect. The paper analysis might predict that a test will cover certain faults, but observation may show that the predicted coverage is not valid when the test actually runs.

Consider AC-coupled differential pairs using coupling capacitors. In some circuits, removing a coupling capacitor will not cause the test to fail. The differential line with an open can capacitively couple across other traces or connector/component pins and still arrive at the differential receiver, albeit with marginal signal integrity. The paper analysis predicted a failure, but the actual test passes in spite of the fault. In actual use, such a board may exhibit intermittent failures.

In another case, tracing through a section of test code might indicate a certain level of coverage, but because of a coding error, that section of the code never actually executes. Again, the paper analysis predicted coverage that did not exist.

The TIG is proposing a methodology that consists of

• reinterpreting functional test in existing structural-coverage terms,
• introducing new coverage elements unique to functional test, and
• reporting functional test coverage in a meaningful and reproducible manner.

The group will apply the methodology to three disparate products—an implantable medical product, an optical networking board, and a PC server board—that offer a range of technologies, complexities, and consequences of failure.

“We’ll exercise our initial methodology on the products,” continued Taylor, “then apply what we learn to fine-tune it, iterating to a usable framework. We will release enough information about our proposed solution and sample results to allow nonparticipating companies to take advantage of our efforts without revealing any proprietary information.”

He cautioned, “Our intention is not to simplify the process, but to create consistency in the industry. Initially, we’ll run statistical reports to establish a baseline. That information will allow us to evaluate the advantages and disadvantages and what the numbers really mean.”

If all goes according to plan, the group’s conclusions should be available by the end of the year.

Boundary scan evolved almost two decades ago to cope with ever-declining access to logic nodes on crowded and complex PCBs (Figure 2). Designers have resisted using the technique because of its design-time overhead and consumption of precious real estate, along with a perception that adopting boundary scan would have a deleterious (if intangible) effect on board “performance.”

Figure 2.  The erosion of electrical access to board nodes for testing is making it more urgent for manufacturers to adopt boundary scan. Source: iNEMI 2007 Test, Inspection, and Measurement Roadmap.  Courtesy of iNEMI.

“When asked why they haven’t embraced the technique more enthusiastically,” Butkovich commented, “component vendors contended that there is no market—not enough demand from individual customers. One purpose of our project is to bring the request to vendors in an industry forum instead of just from a few individual companies. That way we give it more weight.”

Advances in device technology have dramatically reduced the validity of the designers’ early arguments, according to Butkovich. “To start with, some of the component vendors who implemented boundary scan didn’t do it very well,” he said. “The extra circuitry might add 4000 or 5000 gates to a device, but as gates have shrunk, the amount of real estate it [boundary scan] consumes has become insignificant. Automated tools have reduced designers’ time to at most a couple of days. The cost premium, once 15%, has fallen to the point where adding boundary scan shouldn’t increase device costs at all.”

Butkovich contends that presenting the need for boundary scan to vendors in an industry forum brings it in at a high level, emphasizing that the capability is essential to test a lot of products. Vendors shouldn’t consider the inclusion of boundary-scan components as a competitive advantage, but rather as a baseline requirement that all product manufacturers should embrace.

Figure 3.  Complex boards like this one with little or no conventional access to logic nodes demand boundary scan to permit a comprehensive test. Courtesy of Cisco.

The project’s initial effort will survey 12 to 15 companies, analyzing the information received to fine-tune a wider survey of as many as 100 companies. The scope of the survey will help let board and system manufacturers know that they aren’t alone—that the need for this capability in the devices they buy is not unique to a single company or a small subset of companies, but is in fact an industry-wide issue.

“This is everyone’s business,” Butkovich insisted. “We want the project to encourage vendors to get proper tools in place to make the transition to routinely producing boundary-scan devices as easy as possible by pinging the device designers themselves. We know what the designers did two years ago by looking at products already on the market. The survey will tell us what is currently in the pipeline.”

The first surveys have already been sent out. Butkovich expects the data-gathering phase to be complete by late September. After that comes the task of publishing the data and disseminating it to the industry at large. He noted that published results will include only trends and statistics, not individual comments, protecting the anonymity of the participants.

Like Taylor, Butkovich found that working with these otherwise highly competitive companies fostered high levels of cooperation and mutual support. “The companies may compete with each other,” he remarked, “but test engineers don’t generally perceive themselves that way. The project isn’t about proprietary information, but addresses methods that everyone can use to raise the quality bar for everybody. By involving iNEMI, we have created a kind of demilitarized zone for moving the industry forward as a whole. It’s one of the reasons companies join iNEMI.”

The move to lead-free solder, combined with the circuit densities and component types found on today’s PCBs, has aggravated the potential consequences of board deformation that occurs during manufacturing, handling, and normal use. The standards established to measure board susceptibility to flexure damage—IPC/JEDEC 9702 and 9704—need updating to reflect these technology changes. In addition, inconsistencies in the ways that manufacturers apply existing strain-test methods create confusion in assessing damage risks. These concerns spawned the Board Flexure Standardization Project, chaired by Reinosa of HP and co-chaired by Alan McAllister of Intel.

Figure 4.  The spherical-bend test provides an accurate picture of how the device will respond to board stress. Courtesy of Hewlett-Packard.

The board-flexure project also plans to address the way that manufacturers present strain specifications. Reinosa put it this way, “There are two ways to express maximum strain—principal strain and diagonal strain. Customers may not understand the distinction. Manufacturers and vendors must express and use strain limits consistently.”

Part of introducing a new strain-measurement standard or modifying an existing one is understanding the factors that affect board strain. Some of the participating companies have already begun this part of the investigation. “We are looking at the effects of various materials and board features, such as board laminates, BGA [ball-grid array] package sizes, and sizes and types of solder pads,” Reinosa remarked. “The results depend on the type of solder, for example. Lead-free solders are stiffer than the leaded variety. When a board deforms, more of the load transfers to the board laminate and the pad interfaces than with tin-lead solder, so manufacturers need to reduce the maximum permissible strain to ensure board quality.

“Whatever recommendations we make to the standards organizations will not define actual strain limits for particular boards, components, or technologies,” Reinosa emphasized. “Every company has to decide the maximum risk level that each board or product can tolerate. Component manufacturers may quote a different strain limit for each BGA they make, so a board’s limit depends on the design, materials, and BGA mix on that board. Even within a company, the limits may depend on each product’s use. Laptops and cellphones, for example, experience much more cyclic strain than would the motherboard in a desktop PC.”

The project’s participants will also likely agree to disagree over failure criteria. Deciding what test results justify failing a board will depend on the characteristics of each product, product line, and specific company guidelines. “For one product, a company may consider any damage as a failure,” Reinosa observed. “Another product or another company might have a different failure criterion.”

To succeed in moving standards forward, the project has to generate, analyze, and present a lot of data. “IPC and JEDEC won’t change their standards unless they can match the proposed changes against real manufacturer experience. The companies involved will have to share their experimental data. The information provided to the public may be more general, but without the specific data, the committees will not take the needed actions.”

Like the other board-level projects, the flexure project runs on a relatively tight schedule. The group plans to present its findings to IPC and JEDEC by the end of 2008. Reinosa expects a decision from those bodies much more quickly than often occurs in standards debates.

“By working through iNEMI,” she said, “by the time we make our proposal, we will have already consolidated numerous contrasting opinions. This type of project also brings together companies with experience in different aspects of the problem under discussion. One company may know more about laminates, another about package sizes, still another may be an expert in solder-joint characteristics. They each will present their findings, and our standards proposal will present a consensus as much as possible.”

Reinosa continued, “We are not looking to mandate or even recommend maximum strain-level standards for board thicknesses, materials, or any other particulars in the manufacturing process itself. Our goal is only to provide a proven methodology for determining strain limits. Currently, OEMs may specify different acceptance criteria to the same contract manufacturers. By offering a new set of standards that reflect the evolution in board technology and methodologies that has occurred since the previous standards were adopted, we hope to help manufacturers provide consistent, predictable performance and reliability of the boards when they reach customers.”