TI touts support for IEEE 1149.7 standard

-- Test & Measurement World, 9/2/2008 10:51:00 AM

Texas Instruments, a member of the IEEE11.9.7 working group, announced that it is actively supporting the ratification of IEEE 1149.7, a new 2-pin test and debug interface standard that employs half the number of pins of the IEEE 1149.1 technology.

Scheduled for ratification in early 2009, the new standard acts as a port into embedded systems to support software development during system design and to support device manufacturing and testing.

The standard targets multi-chip SOC architectures found in handheld and consumer electronics. With 1149.7, developers could test and debug mobile and handheld communication devices with complex digital circuitry, multiple CPUs, and applications software. TI said it is also working with Freescale Semiconductor, Intel, Lauterbach Datentechnik, IPExtreme, Asset InterTech, Corelis, and GlobeTech Solutions to refine and identify implementation challenges and promote industry-wide adoption.

“The IEEE 1149.7 test and debug technology will be a milestone for the electronics industry by allowing engineers to easily update their current designs to the new standard while preserving investments and compatibility with existing IP modules and tooling,” said Stephen Lau, emulation technology product manager at TI. “TI is joined by leading companies such as Freescale, Intel, and STMicroelectronics in the industry-wide adoption and integration of this technology into our products.”

"Reducing pin count is an important technology to enable advanced mobile devices," said Rolf Kühnis of Nokia, who chairs the Mobile Industry Processor Interface (MIPISM) Test and Debug working group. "IEEE 1149.7 is a standardized, reduced pin interface which is compatible with existing technologies and addresses multi-chip debug challenges. This is why IEEE 1149.7 is recommended in the MIPISM test and debug specifications."

www.ti.com

Talkback

We would love your feedback!

Post a comment

» VIEW ALL TALKBACK THREADS

Related Content

• Topics
• Author

Related Content

 

By This Author

There are no other articles written by this author.

Sponsored Links

TMW Resource Center

Browse Resources by Type:

• Case Study
• Design Guide
• Evaluation Kit
• Web Event
• White Paper

• Optimize Test Coverage with Top 10 Design Hints from JTAG Technologies
  JTAG Technologies | Design Guide
  VIEW NOW
• TMWRC_Averna_122308_WE_Back-to-Basics: Channel modeling and 'what if' analysis for signal integrity applications
  Agilent Technologies | Web Event
  VIEW NOW
• 7 Ways A New Test Engineering Platform Will Help You Cut Costs In 2009
  Averna | Web Event
  VIEW NOW

View More