Time to break away from "big iron"?
In a recent interview, John VanNewkirk of CheckSum discussed new technologies for board test and onboard programming.
By Larry Maloney, Contributing Editor -- Test & Measurement World, 10/1/2008
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Q: How has growing electronics complexity increased the challenges in board test?
A: With surface mount, system-on-chip, and other innovations, density has increased to the point where we often lack sufficient access for test. The result is that in-circuit testers are challenged to provide the 90% coverage we saw years ago. The second issue is the increased use of ISP (in-system programmable) chips, seen in such devices as embedded microcontrollers, flash, and FPGAs (field-programmable gate arrays). Lastly, more manufacturers are building many boards at the same time. Combine these multiboard panels with use of ISP devices and you’ve got a tremendous manufacturing challenge. It’s remarkable that yields in board test have improved substantially over the past decade, despite this complexity.
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John VanNewkirk addresses more questions dealing with onboard programming and lower-cost ICT systems, in the continuation of this interview. |
Q: What changes do you see in the kinds of defects that crop up?
A: Overall, the number of defects has dropped in half over the last decade, but the make-up of the fault spectrum has changed. Solder-related defects have actually grown significantly over the last 10 years with the predominance of surface-mount and very fine-pitch devices. You also see more mechanical-related defects linked to surface mount. For example, a capacitor might pass an electrical test, yet not be located precisely on the board.
On the other hand, digital device defects, which used to account for up to a third of all defects in the mid-’90s, have declined to almost nothing. In a study of five of its biggest plants, Jabil Circuit found that only one board out of 2200 had a digital device failure.
This data confirms what test engineers already knew when they decided to drop digital vector test. So the question is: How far should manufacturers go in their test investment to catch a defect at ICT (in-circuit test) that occurs so rarely, when the defect will still be caught at functional test?
Q: In this environment, what is the place of high-end in-circuit testers?
A: The issue I have with these so-called “big-iron” testers has more to do with economics than technology. These testers have been doing a good job for 20 years in catching defects. The problem comes in the pain they cause manufacturers. Fixtures and programming can cost twice as much as they do for lower-cost ICT. You also have issues with maintenance and training, which can be a major problem at plants in developing countries where you often don’t have people who have spent months in training courses.
Q: What keeps manufacturers from opting for lower-cost solutions?
A: There is still a huge group of electronic manufacturers who have an installed base of expensive ICT platforms and are reluctant to try new technologies. They view ICT as a solved problem. Although they may have excess ICT capacity and shrinking profit margins, some of these firms are simply unwilling to change.
Q: How do you change that mindset?
A: We appeal to the technical needs of engineers and focus on areas that cause pain, such as in-system programming of chips. CheckSum invented the MultiWriter onboard system that can program up to 384 ISP chips at the same time, usually in seconds instead of the minutes required by conventional ICT programmers. For customers that have panels of boards and need high throughput, this is a technique that offers great advantages. MultiWriter has prompted more companies to look at CheckSum, giving us the opportunity to show our other products, such as low-cost ICT platforms.
Read the continuation of this interview.


























