IMEC demonstrates 3-D stacked integrated circuits
Rick Nelson, Editor-in-Chief -- Test & Measurement World, 10/20/2008 7:04:00 AM
LEUVEN, BELGIUM. IMEC has announced that it has made significant progress with its 3D-SIC (3-D stacked IC) technology, having demonstrated its first functional 3-D ICs obtained by die-to-die stacking using 5-micron Cu TSVs (copper through-silicon vias). Engineers speaking at the IMEC Annual Research Review Meeting (ARRM) October 13 described the 3-D technology and outlined the design and test challenges 3-D circuits impose.
Eric Beyne, IMEC scientific director for 3-D technologies, reported that the dies in the demonstration were realized on 200-mm wafers in IMEC’s reference 0.13-micron CMOS process with an added Cu-TSVs process. For stacking, the top die was thinned down to 25 microns and bonded to the landing die by Cu-Cu thermocompression. IMEC, Beyne said, is upscaling the process for die-to-wafer bonding and is on track for migrating the process to its 300-mm platform.
To evaluate the impact of the 3D SIC flow on the characteristics of the stacked layers, Beyne said, both the top and landing wafers contained parametric test structures for TSV characterization, CMOS ring oscillators, and other small functional circuits. Tests, he said, confirmed that the performance of the circuits does not degrade when Cu TSVs are added and the dies are stacked.
Also speaking at the ARRM, Pol Marchal, principal scientist at IMEC working on all aspects of design of digital systems, with a special emphasis on 3-D design and technology-aware design techniques for low-power systems, described the design and test challenges that 3-D structures impose. To extract value from 3-D, he said, engineers must rethink system architectures, employing a physical-aware system-exploration approach. Questions that must be answered range from partitioning (where, for example, to put memory, logic, and RF functions) to test (whether to use BIST or JTAG). Other questions, he said, center on heat dissipation, manufacturability, and reliability.
Marchal proposed the use of IMEC’s PathFinding virtual design flow to help explore the physical design impact of various design options. The PathFinding flow, he said, works with TCAD models and a set of virtual design rules to provide spatially aware estimates of performance and power. He concluded by describing a 3-D stacked-DRAM implementation used to fine-tune IMEC’s technology and to demonstrate the feasibility of 3-D design.
The IMEC 3-D approach presents some test and reliability challenges that are largely absent from 2-D ICs or traditional multichip packages where the dies are interconnected by wire bonds. Beyne pointed out that the dies must be singulated, a process that can generate potentially troublesome particles. (With modern 2-D approaches, process variation—not particle contamination—can cause the most problems.) That complicates the “known good die” problem—the difficulty of ensuring that each die in a multidie package is good before package assembly. Beyne noted that most 3-D approaches would probably involve die-on-die or die-on-wafer fabrication—wafer-on-wafer, he said, would result in too many good dies mated to bad ones. Beyne said that IDDQ tests may be an effective way to screen out bad dies at the wafer level with full test coverage deferred until final multi-die package test.
Beyne said that IMEC is ready to accept reference test circuits from its industry partners to enable them to gain early insight and experience with 3D SIC design. IMEC will provide further details on its 3-D technology at a 3-D integration workshop scheduled for November 13 and 14 in Hsinchu, Taiwan.
www.imec.be
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