Analog effects complicate digital test

The term “analog” conjures up visions of op amps and data converters, but Navraj Nandra, director of marketing for mixed-signal IP at Synopsys, explains that “The speeds of today's chips' serial digital I/O lines ensure that analog effects come into play” even in ostensibly all-digital parts. Complicating matters, he said, is that pure analog companies have the luxury of implementing functions in processes optimized for analog circuitry. In contrast, companies making digital chips want to implement their high-speed I/O in standard deep-submicron digital processes—with all the attendant process-variation and signal-integrity issues.

An eye-diagram mask test illustrates the performance of Synopsys PHY IP for PCI Express 2.0. The diagram can be directly observed on an oscilloscope from a demo board; for production test, an internal sampling-scope function makes the eye diagram available to a standard digital ATE system via a JTAG port. Courtesy of Synopsys.

Of course, IP isn't useful if it isn't testable—in the lab or on the production floor. For lab tests, Synopsys obtains split-lot samples from foundries and evaluates them using demo boards, performing eye-diagram mask tests using bench oscilloscopes (figure). For production test, Synopsys builds diagnostic IP into its PHYs—essentially on-chip sampling oscilloscopes accessible via a JTAG port, enabling a conventional digital tester to perform real-time eye-diagram mask testing.

The Synopsys Website provides a video demo of a lab test of a PCI Express 2.0 PHY device: www.synopsys.com/products/designware. 

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For more information, see “Handcrafted analog gets automated assist” by Rick Nelson, from the September 4 issue of sibling publication EDN.

In Nandra's August 21 EDN article, “On-chip test capabilities solve the analog test problem for high-speed serial interfaces,” he provides details on automating eye-mask tests using a digital production tester.