ITC 2008: Cadence assists Hitachi with 300X compression, Moai with fast tapeout
-- Test & Measurement World, 11/3/2008 9:53:00 AM
Cadence Design Systems at the International Test Conference said Hitachi has combined Encounter Test pattern-fault modeling with test pattern generation, compression, and diagnostics to produce LSI devices for telecommunications and other applications. Cadence also said that Moai Electronics, an IC design company in Taiwan, has deployed Cadence Encounter RTL Compiler and Encounter Test to successfully tape out a flash memory controller.
Cadence said it worked in conjunction with Hitachi to combine Cadence’s pattern fault modeling technology, SDF-based dynamic test generation, and OPMISR+ compression technology with Hitachi’s test methodology to produce test-vector compression results exceeding 300X, a compression level that, Cadence said, matches industry compression requirements set for 2011, according to an ITRS industry survey published in 2007. In addition, Cadence reported, the test coverage results for single-stuck-at-fault, delay-based, and bridge fault exceeded Hitachi's requirements.
“Through the Cadence Encounter Test pattern fault model and advanced test compression technology, we were able to achieve better test quality and meet our test cost requirements,” said Toru Hiyama, GM of the Hardware MONOZUKURI Division at Hitachi. “Our requirements were extremely aggressive, with challenges requiring advanced knowledge and leading technology capabilities, so we were really happy when the Encounter Test team was able to come through.”
Moai design team improves RTL to ATPG turnaround time
Cadence also said that the joint use of Encounter RTL Compiler global synthesis and Encounter Test enabled Moai Electronics’ design team to improve the RTL to ATPG turnaround time from weeks to days. The single flow for logic and DFT synthesis provided greater design optimization, ease of use, and increased productivity, Cadence reported. The advanced fault modeling capability and flexible compression strategy provided higher quality while meeting aggressive tester pin-count cost goals.
“With Encounter RTL Compiler and Encounter Test, we are able to reduce test data volume and test application time and achieve better timing convergence during physical implementation,” said P. F. Lin, president of Moai.
www.cadence.com
www.hitachi.com
www.moai.com.tw
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