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MIT researchers develop finer lines for microchips
July 16, 2008

Massachusetts Institute of Technology (MIT) has reported that researchers have made significant advances in nanoscale lithographic technology, which is used in the manufacturing of computer chips and other electronic devices. These developments have enabled finer patterns of lines over larger areas than previously possible.

The technique developed may lead the way to the next generation of computer memory, integrated circuit chips, advanced solar cells, etc.

The research team has developed lines approximately 25 nanometers wide, which are separated by 25 nm spaces. As of now, the most commercially available chip has a minimum feature of 65nm, and Intel has recently announced that it will begin manufacturing at the 32 nm minimum line-width scale in 2009.

This newly developed technique may also present a more economical approach. This is due to the fact that the process works without the chemically amplified resists, immersion lithography techniques, and the expensive lithography tools that are generally considered essential to work at this scale of optical lithography.

The MIT research team includes Mark Schattenburg and Ralf Heilmann of the MIT Kavli Institute of Astrophysics and Space Research and graduate students Chih-Hao Chang and Yong Zhao of the Department of Mechanical Engineering.

While the technique known as Interference lithography (IL) was used to generate the patterns, they were able to do this by using a nanoruler, a tool built by MIT graduate students. A nanoruler is designed to perform a high precision variant of IL called scanning-beam interference lithography (SBIL).

The SBIL technique has allowed the precision and repeatable pattern registration and overlay over large areas for the first time. This is due to a new, high-precision phase detection algorithm developed by Zhao and an image reversal process developed by Chang.

The research was performed in the Space nanotechnology Laboratory of the MIT Kalvi Institute with financial support from NASA an NSF.  


Posted by Melissa D'Amico on July 16, 2008 | Comments (4)


July 20, 2008
In response to: MIT researchers develop finer lines for microchips
B commented:

Wow, how uninteresting. Let me know when they really accomplish something like create lines 20 nanometers wide. I'm just kidding of course. This is a very fascinating topic and I find it amazing how with new technology we can fit more into smaller spaces. Not to mention, this new innovative method works without the expensive process used in previous techniques. I <3 Interference Lithography




July 21, 2008
In response to: MIT researchers develop finer lines for microchips
Mark commented:

Sounds useful for large arrays, especially if you can build memristors with it and make really cheap non-volatile memory.




July 21, 2008
In response to: MIT researchers develop finer lines for microchips
Mark commented:

Sounds useful for large arrays, especially if you can build memristors with it and make really cheap non-volatile memory.




July 22, 2008
In response to: MIT researchers develop finer lines for microchips
Joe Krasucki commented:

Great work with a clever way of shrinking line widths & spaces..Q :What is the defect density over what area ?? That could determine the yield and ultimately the viability of utilizing these narrow lines.. Another unrelated general Q: As the size and current gets lower and lower, without adequate shielding, microchips become more and more vulnerable to EMP from natural or man-made sources.. e.g from solar flares up to nuclear events at certain altitudes.. The economic and social consequences would be catastrophic. How can we better insure against this type of outcome??





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