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ITC: Behind Closed Doors with Test Experts
October 25, 2006
Santa Clara, CA. The International Test Conference got off to a rousing start as panelists and audience members grappled with tough test issues ranging from whether silicon is free to the value of small-delay-defect testing.
Moderator Ed McCluskey of Stanford University lead the discussion as organizer R. Kapur of Synopsys tried to keep speakers to their 2-minute time limits with the aid of a bicycle horn.
The panel format pitted two teams of experts against each other: Team 1, consisting of Maurice Lousberg of NXP Semiconductors (http://www.nxp.com) and T.W. Williams of Synopsys (http://www.synopsys.com), vs. Team A, fielding Carl Barnhart of SiliconAid Solutions (http://www.siliconaid.com/) and Rob Aitken of ARM (http://www.arm.com). McCluskey encouraged audience members to vote in an electoral process that would have made Florida’s Katherine Harris proud. So in this post I’m not reporting results.
Also, I am not going to attribute specific positions to either team. In fact, often I wasn’t sure whether any one speaker was truly committed to a position or merely playing devil’s advocate. But here are the issues raised and some responses. Panelists and audience members are encouraged to use the
comments link to take credit for or vehemently disavow any viewpoints. (Reader comments are welcome as well.)
Is silicon free? Position 1: Of course it’s not. It may be nearly free in terms of cost per unit area, but every DFT or BIST transistor you lay down contributes to yield loss and power consumption. Position 2: It may not be free, but it’s much cheaper than the extra wires you’ll need to add for test access if you omit DFT and BIST.
Can we reduce false fails? Position 1: We can’t eliminate false fails. Position 2: yes we can, just ship everything.
Can we have an effective multivendor DFT flow? Positions 1 and 2: We are pretty much stuck with multivendor flows and just have to figure out how to make them work.
Do we need burn-in just for qualification or for production as well? Position 1: The ITRS roadmap suggests burn-in will be mandatory because traditional techniques like Iddq test won’t find emerging defect mechanisms. Position 2: Burn-in induces failures that would otherwise never have occurred.
Is tester cost important? Position 1: Initial tester purchase price is an insignificant portion of total test operational costs. Position 2: Testers cost $2,000,000.
Is STIL a useful standard? Position 1: We will always have several dialects but it’s our job as test engineers to make them work. Position 2: STIL is an overly broad standard that has tried to do to much; it has failed and needs to be replaced.
And the winner for most contentious question:
Is small delay test important? Position 1: Once you’ve optimized stuck-at coverage, you must add small delay test to ensure reliability. Position 2: Statistical timing analysis makes small delay test unnecessary. Position 3: Use on-chip test-clock generation. Position 4: On-chip clock generation won’t detect small delay defects. Position 5: If the part passes functional test, who cares if there are small delay defects? Position 6: If you’ve optimized your paths, small delay test becomes equivalent to transition-fault tests. Position 7 (from a recent college graduate): If small delay test is not important, please omit it from the graduate school curriculum!
Posted by Rick Nelson on October 25, 2006 | Comments (4)
