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The incredible shrinking chip
December 20, 2005

The online magazine Slate today inadvertently presents the paradox of the chip that's smaller than each of the hundreds of millions of transistors that populate it. Arguing that the end of Moore's Law is near, Adam L. Penenberg, an assistant professor at New York University and assistant director of the business and economic reporting program in the school's department of journalism, makes this claim:

"Today, Intel can cram almost 1 billion transistors on a microchip that is less than 100 nanometers in size." At least, that's the version posted as of 4:23 p.m. EST December 20, 2005; I expect it will be corrected soon.

First, I assume he's means "a microchip that measures less than 100 nanometers by 100 nanometers." That is pretty small all right, and if Intel is putting 1 billion transistors on such a chip--well, that's a really big story that I somehow missed.

Of course, the size of the chip isn't the issue; it's the approximate size of the smallest line widths used to fabricate each of those hundreds of millions of transistors--which are indeed at sub-100-nanometer levels now. The microchips themselves are much much larger.

Penenberg raises valid points about the difficulties of fabricating deep-submicron chips: excessive heat generation, for example, but even there he misses the mark. Heat is a function of switching speed, not feature size. (Granted, a benefit of reduced feature size is increased speed, which leads to increased heat.)

Ultimately, his failure to grasp the basic concept limits his credibility on the subject. He suggests that 90 nanometers is a "wall" that can't be surpassed. Tell that to the companies perfecting 65- and 45-nanometer technologies.

In Penenberg's defense I will say that the way we refer to semiconductor technology nodes does leave some room for misinterpretation.

Posted by Rick Nelson on December 20, 2005 | Comments (0)