Rick Nelson

RTL test objects at ITC
November 2, 2007

Testability strategies able to handle 65-nm and denser processes highlighted EDA firms’ presentations at last week’s International Test Conference. In particular, power-aware and small-delay-defect test tools grabbed attention as Synopsys announced availability of its TetraMAX small-delay-defect automatic test pattern generator (ATPG) as well as extended low-power-management capabilities within the Synopsys Galaxy environment.

In addition, Cadence reported that companies including K-micro, LSI, G2 Microsystems, and IBM have made use of Cadence’s timing-aware, power-aware, and small-delay-defect test tools. Also on the EDA front at ITC, Mentor Graphics highlighted the recently introduced Xpress enhancement of its TestKompress product (which debuted in 2001); Xpress increases the achievable level of compression by providing an efficient way to handle so-called “X-states.” For memory applications, Virage Logic introduced a version of its Self Test and Repair (STAR) system, adding a dashboard of user-selectable options and adding features that address memory-device yield.

For its part, Magma Design Automation highlighted its new Talus ATPG and Talus ATPG-X and invited Dr. Mohammad Tehranipoor of the University of Connecticut and Brad Lindstrom of Comtech AHA to comment on today’s test issues at a luncheon presentation. Magma CEO Rajeev Madhavan concluded the event by saying, “We envision a flow where test objects inserted at RTL level.”

Already offering scan-test structure insertion at the register transfer level is start-up DeFacTo Technologies, which introduced its HiDFT-Scan tool, which works within existing design flows and with industry-standard synthesis tools.

Read complete International Test Conference coverage.

Posted by Rick Nelson on November 2, 2007 | Comments (0)