Rick Nelson

Semicon Europa workshop addressed test-cocktail limits
October 19, 2007

Traditional test approaches are failing to keep pace with the requirements of dense, complex devices, according to comments from participants in the 9th European Manufacturing Test Conference, held October 9 in Stuttgart, Germany, in conjunction with Semicon Europa. Conference chair Rene Segers of NXP Semiconductors kicked off the workshop by noting that the traditional digital test cocktail, consisting of ATPG plus delay and IDDQ tests, is running out of steam. Further, he said, analog test remains an art that resists structural-test approaches.

During the day-long workshop, engineers representing test vendors as well as semiconductor makers described efforts to extend test to meet today’s needs. Software will have a key role to play, according to keynote speaker Dan Glotter, CEO of OptimalTest. He, in conjunction with consultant Jeff Bibbee, proposed that enterprise test management software can improve yield by 1 to 4% (by reclaiming false fails) and reduce DPPM levels by 20 to 50% while also reducing test time and improving test resource usage efficiency.

But software alone won’t solve all emerging test challenges, and additional workshop presenters described a variety of approaches to improving test processes:

• Stephane Mougin, a product engineering manager at STMicroelectronics, described the application of a Credence Sapphire test system in a multiple-time-domain approach to improving test quality while reducing test cost.

• Enrique De Guzman, a test engineer at AMI Semiconductor Philippines, discussed the impact of test-handler temperature characteristics when testing temperature-sensitive devices. He concluded that the optimization of handler soak time can improve both yield and test capacity.

• Peter Hotz, a field product specialist for RF test at Teradyne, described the use of field solvers and evaluation PCBs for developing best practices for RF device-interface-board layout.

• Joachim Moerbt, department manager responsible for mechatronics activities at Advantest Europe, describes a flexible high-arallel device interface for testing DRAM modules at 400 MHz.

• Jerry Broz, senior applications engineer at International Test Solutions and general chair of the IEEE Semiconductor Wafer Test Workshop, described off-line methodologies for assessing online wafer-probe contact-resistance performance to optimize cleaning protocols.

• Klaus Giringer, division manager of Feinmetall’s probe-card business, commented on meeting the challenges presented by the increasing forces required for full wafer probing of 300-mm wafers in memory and flip-chip applications.

• Robert Rogers, GM for vertical-probe-card products at Wentworth Laboratories, described multi-DUT logic testing in bond-pad and flip-chip applications.

Finally, Ajay Khoche, lead consultant for advanced test methodologies at Verigy—in recognition of that facts that faults will never completely go away and also in recognition of the fact that the logging of structural failure information will be critical for driving yield improvements—described efforts toward using the Standard Test Data Format (STDF) to streamline test-failure dataflow to enhance volume diagnostics.

The ultimate lesson of the workshop seems to be that no one hardware or software solution will suffice to contend with all DUT fault mechanisms. To meet emerging test challenges, test vendors and their customers will need to collaborate to enhance existing test cocktails while developing new test techniques.

Posted by Rick Nelson on October 19, 2007 | Comments (0)