Network measurement timing from master to slave

When Ethernet-based measurements systems call fro precise timing, engineers can use instruments and network switches that IEEE 1588-2008 to synchronize clocks. The LXI Standard includes an option for IEEE 1588.To get the most out of IEEE 1588 in your instrumentation network, you need Ethernet switches that support the standard. These switches use a transparent clock that minimizes latency and delays in the network by providing a local clock for network nodes rather that letting instruments rely on the IEEE master clock.

Researchers at the School of Electrical Engineering and Computer Science at Seoul National University in Korea set out to prove how a transparent clock can minimize timing with errors as low as 30 ns that result goes beyond the 100-ns error tolerance specified in IEEE 1588. The paper, called “A practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems,” explains the measurement technique in detail.

The IEEE 1588 master clock and Ethernet switches use an FPGA developed by the researchers to implement the transparent clock. They then compared the timing errors between identical network configurations using switches with and without the transparent clock. Using a-four-channel oscilloscope, the researchers found maximum errors about 30 ns with the transparent clock (see figure). When using standard Ethernet switches, errors increased by 1000x to 30 µs for slave 3. The network used gigabit Ethernet running at 50% capacity. Without traffic, timing errors for slave 3 were about 500 ns.

The FPGA consists of the Ethernet switch fabric, transmitter, receiver, clock, and MAC (Media access control). A GMII (gigabit media-independent interface) connects the functional blocks to a PHY (physical-layer interface) IC. The paper’s authors report that the network latency varies depending on the PHY manufacturer, which adds a few cycles of timing uncertainty to the measurements.