Cascade addresses high-frequency test, studies TSVs and other emerging technologies

Beaverton, OR. The economic downturn is a good time to focus on R&D, and Cascade Microtech is taking advantage of the current economic situation to help its customers characterize high-frequency devices while investigating the challenges posed by through-silicon vias and other emerging disruptive technologies. That’s the message from an interview with Cascade president and CEO Geoff Wild, followed up by discussion with the company’s CTO, VP of engineering, and VP of marketing.

Demand for 300-mm production equipment has been hard hit, Wild noted, but he added he is seeing resilience in the market for the 150- and 200-mm systems that Cascade provides to engineers. He said he sees demand for probe equipment being driven in part by the growing requirements for KGD (known good die) in multichip packages.

Wild said Cascade, which makes engineering test stations, probes, and sockets as well as production probe cards and sockets, has a good cash position with which to ride out the recession and a strong development pipeline. He said it’s important to emphasize R&D during a recession to address customers’ future technological requirements while controlling cost of ownership. He added that a dialog with customers is critical and that “now is a good time to have that discussion, when people are not rushing around.”

As for application areas, he said Cascade’s competence in high-frequency test should serve the firm well, and he cited work with Roos Instruments on 80-GHz wafer test.

In a wide ranging discussion, founder and CTO Eric Strid, engineering VP Steve Harris, and VP of marketing Mike Kondrat elaborated on Cascade’s products and technologies and commented on the test industry in general.

Kondrat echoed Wild’s enthusiasm for high-frequency measurements, also citing the partnership with Roos Instruments that involves Cascade engineering probes and production probe cards paired with Roos Instruments’ ATE platforms and instrument modules. Cascade, he said, received several requests regarding test of automotive radar devices that operate at 77 GHz. He said experiments demonstrated that Cascade’s Pyramid probes could support 80-GHz measurements in a production environment, giving customers a path from engineering characterization to production test using the same basic probe technology.

Strid noted that as the semiconductor industry has been driven by Moore’s law, Cascade, for the past two decades, has provided the leading-edge tools that are used to measure the DC and RF parameters necessary to derive Spice models. But he cited an example of the pressure now working against Moore’s law: “Somewhere around 45 nm, you are down to one or two molecules of silicon dioxide, and [your process] doesn’t scale anymore.” That’s prompted semiconductor manufacturers to look toward different, higher k, materials like hafnium. Experimentation with such materials, he said, has led customers to make use of some of Cascade’s engineering tools—such as microchamber stations, which he called “the workhorses of engineering labs for measuring really low current levels.” He added, “It’s a continuing struggle for our customers to integrate new materials, and all the new processes and materials require new characterization steps,” such as 1/f noise (or flicker noise) measurement. He noted that repeatability becomes a problem at very low current levels, saying you need at least 500 carriers flowing in a logic gate to get meaningful statistical results.

Kondrat elaborated: “To add to what Eric was saying, modeling as the processes get smaller and smaller becomes more statistically based, and engineers have to measure more and more parameters—I think it’s up to 200 parameters that you have to measure when you are coming out with a new process and series of transistors just derive the Spice models.” And because of the statistical effects, he said, “You have to take a lot of data, you have to do it over many wafers, and you have to do it over temperature.”

Harris elaborated on Strid’s comment about Moore’s law: “Eric pointed out that the scaling only works down to some levels, so continuing down the path of Moore’s law is going to require more innovation towards the back end of the packaging, which has not been the place where the innovation has occurred as much in the past.” In fact, said Strid, devices are “all interconnect limited at this point. The interconnect layers dominate [a device’s] speed, power, and dissipation. Two thirds of the mask layers are already interconnects.”

Strid added that designers and test engineers also must contend with the high-speed lines that get signals from chip to chip and board to board. Implementing 3-D structures, he said, is one approach at the chip level to improving chip-to-chip communications. “Some people would say that in ten years the only DRAM in your PC will be stacked right on top of the microprocessor.” The only other memory, he said, will be in the form of a flash drive. He noted that Cascade has experience building engineering systems for characterizing memory, but as for testing DRAM stacked with other chips, “Exactly how to test those is TBD. It’s not clear they will be tested in historical ways.”

Kondrat suggested additional technology requirements that will pose test challenges. He pointed out that the ITRS roadmap mentions integrating physical sensors into chips, and Kondrat said Cascade will need to add capability for testing pressure, acceleration, and temperature signals.  That, he said, will generate opportunities in both the probe and socket businesses.

Harris pointed out another disruptive technology—wafer-level chip-scale packaging. Socket makers, he said, are looking at their contactor technology and asking how they adapt to test this new CSP technology. The solder balls are 400 to 500 microns, he said, so the contactor makers have a pretty easy time of hitting them. They can do one die test, he said, but the question remains, can they test eight or 16?

Strid noted that this situation leads to a blurring of the line between socket and probe technology. In fact, he questioned the need for separate conferences—Semiconductor Wafer Test Workshop (SWTW) and Burn-in and Test Scoket Workshop (BiTS)—to address probes and sockets, respectively: “It’s surprising that [organizers] separated those two, because I saw [the technologies] merging eventually.” Even back ten years ago, he said, people were asking for multisite, overgrown socket solutions that would perform strip test on a dozen of chips at a time. Ultimately, Strid said, “The customer says, ‘I’m going to wafer-level CSP,’ and he doesn’t care whether he’s using a probe or socket.” As for probe and socket approaches, he said, “There are other synergies—it’s all about contacting small things.”

Kondrat pointed out that Cascade operates at the interface between the device under test and the instrument and provides application support in conjunction with the instrument makers to ensure signal and measurement quality. He added that recently, with the EDGE system, Cascade started bundling instruments in order to provide full control of the measurement environment—primarily noise and temperature. With this approach, he said, customers can make accurate measurements without requiring many hours of application support.

Strid reemphasized that test challenges are growing. “When IC designers need to see an analog voltage on an IC, “they go to extreme extents to bore holes through the back side” and do whatever it takes to keep the device working long enough so they can make the measurement. In contrast, he said, 10 years ago they would just strip off some oxide and poke around, but he added, “Now, if you loading a signal with more than 5 or 10 fF, the signal’s gone. So there’s less observability.”

Engineering VP Harris cited through-silicon vias (TSVs) as a technology that will affect Cascade’s systems business as well as its engineering probes business. “TSVs impact all of our businesses from the standpoint of being able to connect to and make measurements on the TSVs.” That, he said, will apply from an engineering standpoint but will also influence known-good-die production test, requiring new probe-card solutions to perform high-frequency, at-speed testing at the wafer level—on both sides of the wafer.

Kondrat explained new structures like TSVs and new packaging technologies will impact sockets as well as probe cards. Silicon vendors, he said, are starting to put solder balls on both sides of a package to accommodate the space requirements of cell phones, for instance. That, he said, solves package designers’ problem of getting packing necessary functionality in a sufficiently small space, but it will cause significant test challenges. “All of a sudden,” he said, “people will be scratching their heads saying, ‘Gee, how can we test this in high-volume production, over temperature, and over hundreds of thousands of insertions?’” Added Strid, “TSVs are a brave new world when it comes to test because people say, ‘Well, we can build this stuff now,’ but I’m not sure people are even thinking about how they are going to test this stuff.”

Editor’s note: This post originally referred to Mike Kondrat as the marketing director, which was incorrect.